Patent
Constant impedance sampling switch for an analog to digital converter
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TLDR
In this paper, the authors propose a sampling switch with a single metal oxide semiconductor (MOS) transistor to selectively couple the input signal to a sampling circuit, where the potential difference between the signal being sampled and the gate potential of the transistor remains substantially constant over a relatively wide range of amplitudes for the analog input signal.Abstract:
A constant impedance sampling switch suitable for a high-frequency analog-to-digital converter, presents a substantially constant impedance to the input signal regardless of the instantaneous level of the input signal. The exemplary sampling switch employs a single metal oxide semiconductor (MOS) transistor to selectively couple the input signal to a sampling circuit. The gate signal for this transistor is generated by circuitry which is disconnected from the gate of the transistor while the transistor is in an non-conductive state. During a sampling interval, the gate signal is boot-strapped by the instantaneous potential of the input signal to render the transistor conductive. Accordingly, the potential difference between the signal being sampled and the gate potential of the transistor remains substantially constant over a relatively wide range of amplitudes for the analog input signal.read more
Citations
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Journal ArticleDOI
A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
A.M. Abo,Paul R. Gray +1 more
TL;DR: In this paper, a 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6/spl mu/m CMOS technology.
Book
Circuit Techniques for Low-Voltage and High-Speed A/D Converters
M. Waltari,Kari Halonen +1 more
TL;DR: In this article, the authors present a number of low voltage low-voltage techniques, including double sampling with a MOS Transistor Switch, clock generation, and switched opAmp technique.
Proceedings ArticleDOI
A 1.5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter
TL;DR: A 1.5 V, 10-bit, 14.3 MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology with emphasis on observing device reliability constraints at low voltage.
Patent
Two-phase bootstrapped CMOS switch drive technique and circuit
Lawrence A. Singer,Todd L. Books +1 more
TL;DR: In this paper, a gate drive voltage for a MOS transistor switch, that receives an input voltage "on" a source terminal, includes a first input that receives the input voltage, a second input that received a bias voltage, and a voltage storage element.
References
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Patent
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Jimmy R. Naylor,Mark A. Shill +1 more
TL;DR: In this article, a divider circuit scaling the analog input signal down to a lower magnitude such that all values of the scaled analog signal are above the ground reference voltage is applied to a source electrode of a sampling MOSFET.
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Gorecki James L,ジエームス・エル・ゴーレツキ +1 more
TL;DR: In this article, a low distortion capacitor sampling circuit includes a sampling MOSFET, the source electrode of which receives a time-varying input voltage to be sampled.
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TL;DR: In this article, a two-phase pump is used to increase the voltage level on an internal capacitive node in closed loop fashion by effecting unidirectional transfers of charge between successive capacitive nodes.