scispace - formally typeset
Patent

Contact sidewall tapering with argon sputtering

Reads0
Chats0
TLDR
In this article, the authors proposed a method for making a contact opening for an integrated circuit having a feature size of about one micrometer or less by first providing a circuit structure having device elements within a semiconductor substate and multilayer insulating layers thereover.
Abstract
The method for making a contact opening for an integrated circuit having a feature size of about one micrometer or less is accomplished by first providing an integrated circuit structure having device elements within a semiconductor substate and multilayer insulating layers thereover. A resist masking layer is formed over the multilayer insulating layer having openings therein in the areas where the contact openings are desired. Isotropic etching is done through a desired thickness portion of multilayer insulating layer. Anisotropic etching is now done through the remaining thickness of multilayer insulating layer to the semiconductor substrate to form the desired contact opening. The resist layer is removed. The structure is subjected to an Argon sputter etching ambient to smooth the sharp corners at the upper surface of multilayer layer and the point where the isotropic etching ended and the anisotropic etching began. It is preferred that soft reactive ion etching be done for a period of less than about 30 seconds after said Argon sputter etching to reduce the increased contact resistance caused by this Argon sputter etching.

read more

Citations
More filters
Patent

Method to slope conductor profile prior to dielectric deposition to improve dielectric step-coverage

TL;DR: In this paper, the top corners of conductive features are preferentially etched compared to the etch rate of the vertical and horizontal surfaces, thereby creating a sloped (prograde) profile.
Patent

Top corner rounding for shallow trench isolation

TL;DR: In this paper, a process for top-corner rounding at the rim of shallow trenches of the type used for STI is described, which is achieved by first forming the trench using a silicon nitride hard mask having a layer of pad oxide between itself and the silicon surface.
Patent

Tapering sidewalls of via holes

TL;DR: In this paper, a method of tapering side walls of via holes and a tapered via hole structure for an integrated circuit is provided, where via holes having steep sidewalls are provided in an insulating layer overlying a conductive layer on a substrate.
Patent

Integration of ALD/CVD barriers with porous low k materials

TL;DR: In this paper, a method for processing substrates is described, which includes depositing and etching a low k dielectric layer on a substrate, pre-cleaning the substrate with a plasma, and depositing a barrier layer on the substrate.
Patent

Buried patterned conductor planes for semiconductor-on-insulator integrated circuit

TL;DR: A semiconductor-on-insulator integrated circuit with buried patterned layers as electrical conductors for discrete device functions, thermal conductors, and/or decoupling capacitors as mentioned in this paper.
References
More filters
Patent

Dry etch of phosphosilicate glass with selectivity to undoped oxide

TL;DR: In this article, an etchant of PSG with high selectivity to substantially undoped oxide (BPSG) was presented, and the etch rate ratio was shown to be 11 to 1.
Patent

Sloped contact etch process

TL;DR: In this paper, the authors described a sloped contact etch, which has the steps of: etching a substrate 12 then removing the polymer that is produced during the substrate 12 etch These two steps are alternated until a desired depth is reached.
Patent

Method of forming a via-hole having a desired slope in a photoresist masked composite insulating layer

TL;DR: In this article, the authors used a plasma action in a gas mixture containing a fluorine compound and an oxidizer with a percentage of the oxidizer of about 10-20% to form a tapered hole having the desired slope in the top PSG insulating layer.
Patent

Integrated circuit process with TiN-gate transistor

TL;DR: In this paper, the authors describe an integrated circuit process which includes forming two types of active devices: a first set of IGFETs has silicide gates, and the second set has TiN gates.
Patent

Process for forming contact openings through oxide layers

TL;DR: In this article, a process for forming an opening for a contact member through a deposited oxide layer and thermally grown oxide layer is described, where a wet etchant is used to etch through the oxide layer.