Proceedings ArticleDOI
Customization of Register File Banking Architecture for Low Power
R. Nalluri,R. Garg,Preeti Ranjan Panda +2 more
- pp 239-244
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TLDR
Experimental results indicate that the customized dual bank configuration inferred by both techniques gives energy savings of 40% over a monolithic register file, and the multi-bank register file customization gives a further 15-20% energy savings.Abstract:
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application specific customization of register file banking structure. First, we propose two techniques based on: (i) profiling; and (ii) static application analysis to arrive at a customized energy-efficient bank configuration for a given application on a dual bank register file. We also propose a technique to extend the exploration to a multi-bank register file architecture and an associated register allocation algorithm for further power reduction. This reduces register file power consumption by allocating variables in frequently accessed basic blocks to separate appropriately sized register file bank of active registers. Experimental results indicate that our customized dual bank configuration inferred by both techniques gives energy savings of 40% over a monolithic register file, and the multi-bank register file customization gives a further 15-20% energy savingsread more
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Journal ArticleDOI
Application-Guided Power Gating Reducing Register File Static Power
Hamed Tabkhi,Gunar Schirner +1 more
TL;DR: This paper introduces an application-guided function-level register file power-gating (AFReP) approach to efficiently manage and reduce the RF's static power consumption and enhances a Blackfin processor with the AFReP technology.
Proceedings ArticleDOI
An Energy-Efficient Unified Register File for Mobile GPUs
TL;DR: The result shows that proposed design reduces 85% of dynamic energy in a multithreaded register file and 59% of leakage energy and 25% of area with negligible performance degradation.
Journal ArticleDOI
A Survey of Techniques for Designing and Managing CPU Register File
TL;DR: A survey of techniques for architecting and managing CPU register file and classify the techniques across several parameters to underscore their similarities and differences.
Proceedings ArticleDOI
Register File customization for low power embedded processors
TL;DR: This paper proposes a customization approach at the hardware description modeling level to reduce the register file power consumption, which does not alter the RF interface to other hardware components and is completely transparent to software code.
Journal ArticleDOI
Customized pipeline and instruction set architecture for embedded processing engines
TL;DR: The proposed architecture increases the performance by enhancing the available registerfile data bandwidth through register access pipelining, and achieves improvements are made by introducing double-word custom instructions whose registerfile accesses are overlapped in the pipeline.
References
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Proceedings ArticleDOI
Register allocation & spilling via graph coloring
TL;DR: This work has discovered how to extend the graph coloring approach so that it naturally solves the spilling problem, and produces better object code and takes much less compile time.
Journal ArticleDOI
Register allocation & spilling via graph coloring
TL;DR: In a previous paper as mentioned in this paper, we reported the successful use of graph coloring techniques for doing global register allocation in an experimental PL/I optimizing compiler, when the compiler cannot color the...
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Drowsy caches: simple techniques for reducing leakage power
TL;DR: It is argued that the use of drowsy caches can simplify the design and control of low-leakage caches, and avoid the need to completely turn off selected cache lines and lose their state.
Journal ArticleDOI
The CRAY-1 computer system
TL;DR: The CRAY-1 is the only computer to have been built to date that satisfies ERDA's Class VI requirement (a computer capable of processing from 20 to 60 million floating point operations per second) and its Fortran compiler (CFT) is designed to give the scientific user immediate access to the benefits of the Cray-1's vector processing architecture.
Proceedings ArticleDOI
Multiple-banked register file architectures
TL;DR: This paper proposes a register file architecture composed of multiple banks, which provides low latency and simple bypass logic and shows that a two-level organization degrades IPC and increases performance by 87% and 92% when the register file access time is factored in.