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CMU-CS-82-115
DESIGN AND IMPLEMENTATION OF A
SINGLE-CHIP 1-D MEDIAN FILTER
Kemal Oflazer
Department of Computer Science
Carnegie-Mellon University
Pittsburgh, PA, 15213
April 1982
ABSTRACT
The design and implementation of a 1-Dimensional median filter in VLSI is presented. The device
is designed to operate on 8-bit sample sequences with a window size of 5 samples. Extensive
pipelining and employment of systolic concepts at the bit level enable the chip to filler at rates up to
10 Mega-samples per second The chip is designed to be implemented with a X =
2.5ji
NMOS
technology and is 6.2 mm by 5.0 mm in size. A circuit configuration for using the chip in
approximate 2-D median filtering is also presented
Copyright © 1982 Kemal Oflazer
This research is supported in part by the Office of Naval Research under Contracts
N00014-76-C-0370,NR 044-0422 and N00014-80-C-0236,NR 048-659, in part by the National Science
Foundation under Grant MCS 78-236-76 , and in part by the Defense Advanced Research Projects Agency
(DOD), ARPA Order No. 3597, monitored by the Air Force Avionics Laboratory under Contract
F33615-81-K-1539.
i
Table of Contents
1.
Introduction
2.
Systolic Algorithms and Structures
3.
The 1-Dimensional Median-Filtering Algorithm
3.1.
High-Level Structure of the Algorithm
3.2. Hardware Implementation of the Algorithm
4.TheChip
5.
Application to 2-Dimensional Image Processing
6. Evaluation and Conclusions
7.
Acknowledgements
r
1
ii
List of Figures
Figure 3-1: High level structure of the algorithm 3
Figure 3-2: The basic compare-and-swap unit 4
Figure 3-3: Internal structure of the odd/even-transposition sort network 6
Figure
4-1:
The floor plan of the chip 7
Figure 5-1: Hardware structure to implement the approximate 2-D median filtering 7
1
1.
Introduction
Median filtering is a nonlinear signal smoothing operation in which the median of a window of size
w = 2n +1 replaces the sample at the middle of the window. Medians computed in this way tend to follow
the polynomial trends in the original sequence while sharp discontinuities of short duration are filtered out
Further properties of median filtering have been described in [1] while [2] describes its application to speech
processing. Recently, an algorithm for real-time median filtering has been presented in [3]. Systolic
algorithms for one- and multi-dimensional median-filtering operations and the more general case of
computing running-order statistics have been recently proposed by Fisher [4].
This work presents the design and implementation of a VLSI chip for the 1-dimensional median-filtering
operation. The device is designed to operate on
8-bit
sample sequences with a window size of 5 samples.
Extensive pipelining and employment of systolic concepts at the bit level enable the chip to have a very high
throughput, i.e. the chip can be clocked at rates up to 10 Mhz and produce one median every clock cycle after
an initial delay to fill the pipeline. The chip is designed to operate as a shift register in a system environment,
filtering data coming from the source before going into the actual computing system.
2.
Systolic Algorithms and Structures
Rapidly advancing VLSI technology offers system designers a very high potential for parallel operations.
However, in order to exploit this potential, algorithms to be implemented with VLSI computing structures
should have regular and simple communication schemes. This is mainly due to the fact that communication,
especially irregular communication, is costly in VLSI in terms of the chip area that communication channels
(i.e.
wires) occupy. Furthermore, to reduce the design time, these algorithms should employ a rather small
number of basic building blocks (or cells) from which larger systems can be built
A class of parallel algorithms that exhibit such regular structures are systolic algorithms. Systolic algorithms
for various computational problems have been described in [4, 5,6,7,8]. Systolic data structures for priority
queue operations and connectivity problems have been proposed in [9] and in [10] respectively. The general
architectural principles of systolic computation systems have been discussed by Kung in [11]. In general,
systolic algorithms and the underlying hardware structures implementing them have very regular neighbor-to-
neighbor communication schemes. They utilize their inputs many times through pipelining and
multi-directional data flow and hence do not make heavy bandwidth demands on system memories.
Employment of systolic concepts at the low-level implementation of logic circuits for various simple
functions (like addition and comparison) also leads to regular structures that have small propagation delays
(independent of the size of the circuit) and require no broadcasting. Such circuits are suitable as building