Patent
Design for a simulation module using an object-oriented programming language
TLDR
In this paper, a register transfer level (RTL) model is created using an object-oriented programming language, where a logic circuit can be represented by a hierarchy of objects ("modules") each having representation of state elements, input signals, output signals and internal signals.Abstract:
A register transfer level (RTL) model is created using an object-oriented programming language. In that RTL model, a logic circuit can be represented by a hierarchy of objects ("modules") each having representation of state elements, input signals, output signals and internal signals. Each object is also provided member functions for initializing, for loading a new state and for generating a next state. These modules are collected in a linked list. In the beginning of simulation, each object is initialized as the linked list is traversed. Then, a consistent next state for the RTL model is obtained by generating a state next based on the initial state. Simulation proceeds by alternately traversing the linked list to load a new state into each module, and traversing the linked list to generate the next state for each module. The step of traversing the linked list to generate the next state of each module may require multiple executions to ensure convergence.read more
Citations
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Patent
System and method for simulation of integrated hardware and software components
TL;DR: In this paper, a cycle-accurate simulator library for modeling and verifying hardware components of a desired electronic device is provided, which includes built-in models and routines for simulating multiple internal hardware components.
Patent
Hardware and software co-simulation including executing an analyzed user program
TL;DR: In this article, a co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via a interface mechanism, where the execution of a user program is simulated by executing an analyzed version of the user program on the host computer.
Patent
Design apparatus and a method for generating an implementable description of a digital system
TL;DR: In this article, the authors present a design apparatus compiled on a computer environment for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for said system, said behavioral description being represented on said computer environment as a first set of objects with a first sets of relations there between, said implementable descriptions being represented as a second set of object with a second sets of relation there between.
Patent
Structured algorithmic programming language approach to system design
TL;DR: An algorithmic programming language approach to system design enables design, synthesis, and validation of structured, system-level specifications, and integrates system level design into the rest of the design process as mentioned in this paper.
Patent
Simulation model using object-oriented programming
TL;DR: In this paper, a method, apparatus and system for simulating the operation of a circuit using a computer-based simulator comprising of distributing at least one signal upon to one or more simulation model subcircuit functions, which use the signal, upon a change in the signal.
References
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Patent
Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models
TL;DR: In this article, an automatic logic-model generation system operates on a behavioral description of an electronic design (e.g., a circuit, a system, etc.) to automatically generate a low-level (i.e., circuit-level) design of the electronic design, to lay out the electronics design for production in the form of an integrated circuit, and to produce logic-level models incorporating accurate timing (and delay) information.
Patent
Method and apparatus to emulate VLSI circuits within a logic simulator
TL;DR: In this article, an emulation modeling apparatus (54) comprises a combination of a device under simulation (48) to be emulated and means for keeping the VLSI circuit in a quiescent state at normal operating speeds and in a normal operating sequence so as to allow dual access to the emulation modelling apparatus without loss of data or accuracy of functions.
Patent
Hardware simulation and design verification system and method
TL;DR: In this article, a hardware design verification system has a hardware simulator, a test script, and a dispatcher, each running as concurrent processes on a computer, and the test script language is independent of the hardware simulator language.
Patent
Method for mapping in logic synthesis by logic classification
Robert F. Damiano,Anthony DeGroff Drumm,Michael Kay Edwards,Robert L. Kanzelman,Kathy M. McCarthy +4 more
TL;DR: In this paper, a method within a logic synthesis system provides for using tags attached to the nodes in a parse string generated from an abstract description of a logic design to classify portions of a heterogeneous design as open control, structure dominant, or direct map.
Proceedings ArticleDOI
High-level synthesis and codesign methods: an application to a videophone codec
Pierre Paulin,Jean Fréhel,Michel Harrand,Elisabeth Berrebi,Clifford Liem,F. Nacabal,Jean-Claude Herluison +6 more
TL;DR: A five-fold reduction in the source HDL description complexity; equal or better timing performance; silicon area within 15% and automatically compiled assembly code (from ANSI C descriptions) that is as compact as hand-coded assembler are shown.