Journal ArticleDOI
Design of FinFET-based Energy Efficient Pass-Transistor Adiabatic Logic for ultra-low power applications
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TLDR
FinFET-based Energy Efficient Pass Transistor Adiabatic Logic powered by four-phase power clock capable of operating up to 1 GHz with low energy dissipation is presented.About:
This article is published in Microelectronics Journal.The article was published on 2019-10-01. It has received 11 citations till now. The article focuses on the topics: Adiabatic circuit & Pass transistor logic.read more
Citations
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Journal ArticleDOI
An efficient multiplier by pass transistor logic partial product and a modified hybrid full adder for image processing applications
TL;DR: The overall results of the multiplier approve its capability for digital signal processors (DSPs) as low-power, high-speed, low power-delay-product (PDP), and high competency of both circuits for using in sophisticated structures like multipliers are confirmed by mathematical relations.
Journal ArticleDOI
VLSI implementation of Wave Shaping Diode based Adiabatic Logic (WSDAL)
Dinesh Kumar,Manoj Kumar +1 more
TL;DR: In this work proposed design of SR flip-flop proved the compatibility of WSDAL for sequential logic also and the new designs perform well at stringent temperature conditions and can be used for low power electronics circuits.
Journal ArticleDOI
Design of 0.8V, 22 nm DG-FinFET based efficient VLSI multiplexers
B. Jeevan,K. Sivani +1 more
TL;DR: This paper proposes a Double Gate (DG) FinFET based 4-1, 8- 1, 16-1 multiplexer (DFMs) with a reduced number of transistors catering to the needs of low-power dissipation and high speed, and simulated results show the proposed DFM multiplexers’ power-delay product is better.
Journal ArticleDOI
Implementation of parallel computing and adiabatic logic in full adder design for ultra-low-power applications
Dinesh Kumar,Manoj Kumar +1 more
TL;DR: A new architecture of full adder has been proposed in which the input needs to pass through only two transistors to reach the output node which results in reduced delay time and the use of adiabatic logic makes these designs energy efficient for low power applications.
Journal ArticleDOI
Design and Implementation of ALU Using Graphene Nanoribbon Field-Effect Transistor and Fin Field-Effect Transistor
TL;DR: In this article , the design and development of hybrid delay-controlled reconfigurable ALU (DCR-ALU) using field-effect transistor (FinFET) and graphene nanoribbon field effect transistor (GnrFET).
References
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Book
FinFETs and Other Multi-Gate Transistors
TL;DR: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FET) and explains the physics and properties.
Journal ArticleDOI
Pass-transistor adiabatic logic using single power-clock supply
TL;DR: In this article, a pass-transistor adiabatic logic (PAL) was proposed to operate from a single power-clock supply and outperforms the previously reported adiabilistic logic techniques in terms of its energy use.
Journal ArticleDOI
Positive feedback in adiabatic logic
TL;DR: In this paper, an adiabatic logic family is presented, which makes use of a CMOS positive feedback amplifier, and a gate is based on dual rail logic and a cascade of such gates only needs three power/clock lines to operate.
Journal ArticleDOI
FinFETs: From Devices to Architectures
D. Bhattacharya,Niraj K. Jha +1 more
TL;DR: Research on FinFETs from the bottommost device level to the topmost architecture level is reviewed and various possible FinFet asymmetries and their impact are surveyed, and novel logic-level and architecture-level tradeoffs offered by FinFetts are surveyed.
Dissertation
Asymptotically zero energy computing using split-level charge recovery logic
TL;DR: New CMOS logic families are presented, including Split-Level Charge Recovery Logic (SCRL), within which the transfer of charge between the nodes occurs quasistatically, thus having a power consumption that drops quadratically with operating frequency as opposed to the linear drop of conventional CMOS.