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Digital frequency shift signal demodulator

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TLDR
In this paper, a zero-crossing detector is used to detect zero crossing of frequency shift signals (FS) in a demodulator, and a determination circuit is employed to discriminate frequency discrimination by comparing the counts of the counter means with a given limit.
Abstract
An FS signal demodulator includes a zero-crossing detector which detects zero-crossings of frequency shift signals (FS), a pulse converter which generates a train of "0" and "1", "0" representative of a time slot from the first detected zero-crossing through a given period of time and "1" representative of a time slot from that period through the next succeeding zero-crossing, a memory means receiving the outputs of the pulse converter and thus containing the train of the pulses with the length corresponding to modulation rate, a counter means counting the number of "1's" or "0's" contained within the memory means in response to clock signals, and a determination circuit which effects frequency discrimination by comparing the counts of the counter means with a given limit.

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Citations
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References
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Digital fsk/psk detector

TL;DR: In this paper, the authors proposed a digital FSK/PSK detector for moderate data rates including at least 1200 bits per second and is capable of operating over switching networks, which consists of a binary amplitude quantizer, a clock, a digital time quantizer and a digital delay coacting with an Exclusive-OR circuit for detecting the digital data signal from the frequency shift keyed modulation signal.
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TL;DR: In this article, a counter whose output is delivered to a digital comparator also receiving a fixed reference number not less than and preferably equal to the count of clock pulses generated during a half-cycle of frequency F A.
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Digital circuit discriminator for frequency-shift data signals

TL;DR: In this paper, a zero-crossing detector produces a pulse for each zero crossing of the binary signal and the pulses are processed by a transversal digital filter having finite memory and arranged to provide triangular weighting to each input pulse.