Don't cares and multi-valued logic network minimization
Yunjian Jiang,Robert K. Brayton +1 more
- pp 520-525
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This work addresses optimizing multi-valued (MV) logic functions in a multi-level combinational logic network and gives a recursive image computation to transform the don't cares into the space of local inputs of the node to be minimized.Abstract:
We address optimizing multi-valued (MV) logic functions in a multi-level combinational logic network. Each node in the network, called an MV-node, has multi-valued inputs and single multi-valued output. The notion of don't cares used in binary logic is generalized to multi-valued logic. It contains two types of flexibility: incomplete specification and non-determinism. We generalize the computation of observability don't cares for a multi-valued function node. Methods are given to compute (a) the maximum set of observability don't cares, and (b) the compatible set of observability don't cares for each MV-node. We give a recursive image computation to transform the don't cares into the space of local inputs of the node to be minimized. The methods are applied to some experimental multi-valued networks, and demonstrate reduction in the size of the tables that represent multi-valued logic functions.read more
Citations
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Proceedings ArticleDOI
HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform
Massimo Baleani,Frank E. Gennari,Yunjian Jiang,Yatish Patel,Robert K. Brayton,Alberto Sangiovanni-Vincentelli +5 more
TL;DR: This paper studies the use of a reconfigurable architecture platform for embedded control applications aimed at improving real time performance and proposes a new mapping flow and algorithms to partition hardware and software that best utilize this architecture.
Proceedings ArticleDOI
SAT-Based Complete Don't-Care Computation for Network Optimization
TL;DR: SAT reduces the runtime and enhances robustness, making don't-cares affordable for a variety of other Boolean methods applied to the network, and gives a SAT-basedDon't-care computation algorithm that is more efficient than BDD-based algorithms.
Book ChapterDOI
Two-level logic minimization
Olivier Coudert,Tsutomu Sasao +1 more
TL;DR: This chapter presents both exact and heuristic two-level logic minimization algorithms, and shows various techniques to reduce the complexity of covering problems and discusses branching heuristics.
Proceedings ArticleDOI
Simplification of non-deterministic multi-valued networks
TL;DR: This work discusses the simplification of non-deterministic MV networks and their internal nodes using internal flexibilities and shows that the flexibility derived is maximum.
Proceedings ArticleDOI
Optimization of multi-valued multi-level networks
M. Gao,J.-H. Jiang,Yunjian Jiang,Y. Li,Alan Mishchenko,Subarna Sinha,Tiziano Villa,Robert K. Brayton +7 more
TL;DR: A program called MVSIS (Multi-Valued Sequential Interactive Synthesis) has been developed which optimizes multi-level multi-valued (MV) networks, and it is described what such a network is and the capabilities contained in MVSis.
References
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Journal Article
SIS : A System for Sequential Circuit Synthesis
TL;DR: This paper provides an overview of SIS and contains descriptions of the input specification, STG (state transition graph) manipulation, new logic optimization and verification algorithms, ASTG (asynchronous signal transition graph] manipulation, and synthesis for PGA’s (programmable gate arrays).
Book ChapterDOI
VIS: A System for Verification and Synthesis
Robert K. Brayton,Gary D. Hachtel,Alberto Sangiovanni-Vincentelli,Fabio Somenzi,Adnan Aziz,Szu-Tsung Cheng,Stephen A. Edwards,Sunil P. Khatri,Yuji Kukimoto,Abelardo Pardo,Shaz Qadeer,Rajeev Kumar Ranjan,Shaker Sarwary,Thomas R. Shiple,Gitanjali Swamy,Tiziano Villa +15 more
TL;DR: VIS provides the capability to check the combinational equivalence of two designs and provides traditional verification in the form of a cycle-based simulator that uses BDD techniques.
Journal ArticleDOI
Multiple-Valued Minimization for PLA Optimization
TL;DR: Results show that the heuristic algorithm Espresso-MV comes very close to producing optimum solutions for most of the examples, and shows how important multiple-valued minimization can be for PLA optimization.
Proceedings ArticleDOI
Algorithms for discrete function manipulation
TL;DR: The authors define the multi-valued decision diagram, analyze its properties and provide algorithms for combining and manipulating MDDs and give a method for mapping an MDD into an equivalent BDD (binary decision diagram) which allows them to provide a highly efficient implementation using the previously developed BDD packages.
Proceedings ArticleDOI
Extracting local don't cares for network optimization
TL;DR: An algorithm for computing local don't cares (in terms of immediate fanin variables) at each intermediate node of a Boolean network is presented and experimental results are presented that show the effectiveness of the proposed algorithm on benchmark circuits with and without externalDon't cares.
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