Patent
Fabrication of FETs
TLDR
In this article, the active channel area is defined by a photoresist pattern, and Ions are implanted into the exposed area in a concentration to achieve a desired threshold in order to control the threshold potential.Abstract:
A method of fabricating field effect transistors which includes control of threshold potential by an ion implantation limited to the active channel area. The active channel area is defined by a photoresist pattern. Ions are implanted into the exposed area in a concentration to achieve a desired threshold. Appropriate metals are deposited over the channel area to form a gate electrode. The photoresist is lifted off leaving the gate electrode in position over the channel area. If desired, a layer of polysilicon can be included prior to resist formation and later removed by an etchant which does not attack the gate electrode.read more
Citations
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Patent
Method of forming metal-strapped polysilicon gate electrode for FET device
TL;DR: In this article, a gate stack is defined on an exposed surface of a semiconductor substrate, the gate stack including a gate mask disposed on a patterned polysilicon layer, and an insulating layer is then formed on the substrate, and is planarized to expose an upper surface of the gate mask.
Patent
Process of making twin well VLSI CMOS
TL;DR: In this paper, a two mask, one photolithographic step process is used as a template to form the second inverse mask of substantially equal thickness, which is then used as alignment mask for shallow source and drain regions.
Patent
Process for manufacturing semiconductor BICMOS device
Tzu-Yin Chiu,Gen M. Chin,Ronald Curtis Hanson,Maureen Y. Lau,Kwing F. Lee,Mark D. Morris,Alexander M Voshchenkov,Avinoam Kornblit,Joseph Lebowitz,William Thomas Lynch +9 more
TL;DR: In this article, a process for creating bipolar and CMOS transistors on a p-type silicon substrate is described, and a wall of silicon dioxide is created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls.
Patent
Integration of an amorphous silicon resistive switching device
Sung Hyun Jo,Hagop Nazarian +1 more
TL;DR: In this paper, an integrated circuit device with a gate dielectric layer overlaying the surface region of the substrate is described, where a MOS device having a p+ active region forms a first electrode for a resistive switching device.
Patent
Threshold adjustment in field effect semiconductor devices
TL;DR: In this paper, the p+ source/drain implant mask is used to restrict the threshold adjust implant to the PMOS devices, thereby avoiding adversely affecting other devices in the integrated circuit.
References
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Patent
Method of controlling MOSFET threshold voltage with self-aligned channel stop
TL;DR: In this paper, the threshold voltage of both the channel and field regions of a MOSFET was controlled by forming a comparatively thick oxide film on a semiconductor surface, defining enhancement mode transistor regions in the oxide film to expose portions of the semiconductor surfaces, implanting p-type ions under conditions such that the peak distribution of ptype atoms lies in the semi-conductor substrate just beneath the semiconductors/oxide interface and counter-doping with n-type ion under conditions that no implanted ions penetrate the oxide films.
Patent
Cobalt silicide metallization for semiconductor integrated circuits
TL;DR: In this paper, a cobalt layer is sintered at about 400° C. to 500° C., on a patterned semiconductor wafer having exposed polycrystalline (14 or monocrystalline) silicon portions, as well as exposed oxide (15 or 25) portions.
Patent
Method of making self-aligned device
TL;DR: In this paper, a self-aligned MOS transistor is constructed using undercut etching of a polycrystalline silicon gate electrode, which allows the source and drain regions to be selfaligned with and closely spaced to the gate electrode.
Patent
Process for selectively forming refractory metal silicide layers on semiconductor devices
Joseph J. Fatula,Stanley Roberts +1 more
TL;DR: In this article, a method of forming a refractory metal silicide pattern on a substrate by forming a blanket layer (12) of Si02 on the substrate, depositing a blanket (14) of polycrystalline Si over the Si02 layer, defining a pattern in the blanket Si layer, and exposing selected areas of the SiO2 layer.
Patent
Method of making contact electrodes to silicon gate, and source and drain regions, of a semiconductor device
Martin P Lepselter,Simon M. Sze +1 more
TL;DR: In this paper, the authors describe the fabrication of a metal oxide semiconductor field effect transistor (MOSFET) or a metal gate MESFET, characterized by a polycrystalline silicon gate and a short channel of about a micron or less.