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Patent

Fast semiconductor digital logic inverter gate

TLDR
In this paper, an extremely fast, highly regulated and non-resistive semiconductor digital logic inverter gate which is suitable for use as a fundamental building block in an uncommitted gate array is presented.
Abstract
An extremely fast, highly regulated and nonresistive semiconductor digital logic inverter gate which is suitable for use as a fundamental building block in an uncommitted gate array includes an input conductor, at least one output conductor, a first current source providing a fixed current of a given magnitude to the input conductor, a second current source providing a current varying exponentially with input voltage to each output conductor, and a current control circuit operating in response to current flow through the input conductor to control the magnitude of current provided by the second source of current to each of the output conductors at a magnitude greater than the first magnitude or at a nonzero magnitude substantially less than the first magnitude. Subnanosecond time delays in switching between digital logic states are attained by constructing the logic gate as an integrated circuit from Schottky diodes which have very little transit time delay and bipolar transistors which are never biased into either saturation or cutoff. Capacitance charging time is minimized by utilizing a small difference in forward bias voltage drops across different kinds of Schottky diodes to clamp digital logic voltage swings at approximately 133 millivolts or less. Because of its exponential voltage current relationship this voltage differential applied across the base emitter terminals of a transistor utilized in the second current source is sufficient to provide current differentials greater than 100:1 for maintenance of a good noise margin.

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Citations
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References
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TTL compatible logic gate circuit

TL;DR: In this paper, a logic gate circuit includes a resistance divider input to the base of an input transistor and a multiple emitter output transistor in an emitter follower configuration, which reduces the effect of both capacitive loading and series resistance in signal interconnections.