Formal verification in a commercial setting
Robert P. Kurshan
- pp 258-262
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This tutorial addresses the following questions: why do formal verification?Abstract:
This tutorial addresses the following questions: why do formal verification? who is doing it today? what are they doing? how are they doing it? what about the future?read more
Citations
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Journal ArticleDOI
Formal verification in hardware design: a survey
TL;DR: A selection of case studies where formal methods were applied to industrial-scale designs, such as microprocessors, floating-point hardware, protocols, memory subsystems, and communications hardware are presented.
Book ChapterDOI
The ForSpec Temporal Logic: A New Temporal Property-Specification Language
Roy Armoni,Limor Fix,Alon Flaisher,Rob Gerth,Boris Ginsburg,Tomer Kanza,Avner Landver,Sela Mador-Haim,Eli Singerman,Andreas Tiemeyer,Moshe Y. Vardi,Yael Zbar +11 more
TL;DR: The ForSpec Temporal Logic (FTL) is the new temporal property-specification logic of ForSpec, Intel's new formal specification language and includes constructs that enable the user to model multiple clock and reset signals, which is useful in the verification of hardware design.
Journal ArticleDOI
Using abstraction and model checking to detect safety violations in requirements specifications
TL;DR: A "practical" formal method that can expose inconsistencies in software requirements specifications and the SCR (software cost reduction) tabular notation is described, which most software developers should be able to apply without extraordinary effort.
Journal ArticleDOI
Model Checking Complete Requirements Specifications Using Abstraction
TL;DR: This paper describes how one can model check a complete requirements specification expressed in the SCR (Software Cost Reduction) tabular notation, and uses model checking to analyze properties of a complete SCR specification with variables ranging over many data types.
Proceedings ArticleDOI
Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
TL;DR: A novel procedure based on uninterpreted symbolic simulation for checking the scheduling step in high-level synthesis and its ability to efficiently handle loops and a wide range of loop transformations performed during scheduling is proposed.
References
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Journal ArticleDOI
Automatic verification of finite-state concurrent systems using temporal logic specifications
TL;DR: It is argued that this technique can provide a practical alternative to manual proof construction or use of a mechanical theorem prover for verifying many finite-state concurrent systems.
Book
Symbolic Model Checking
TL;DR: Using symbolic model checking techniques it is possible to verify industrial-size finite state systems and models with more than 10120 states have been verified using special techniques.
Book
Design and validation of computer protocols
TL;DR: Part 1 Basic: introduction protocol structure error control flow control and design tools: a protocol simulator a protocol validator using the validator.
Book
Computer-Aided Verification of Coordinating Processes: The Automata-Theoretic Approach
TL;DR: Theories of L-automaton/L-process, L-matrix, and String Acceptors are compared to Boolean Algebra, which describes the construction of language-based Algebra.
Journal ArticleDOI
Symbolic model checking for sequential circuit verification
TL;DR: In this paper, the temporal logic model checking algorithm of Clarke, Emerson, and Sistla is modified to represent state graphs using binary decision diagrams (BDD's) and partitioned transition relations.