Patent
Forming memory transistors with varying gate oxide thicknesses
TLDR
A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS-type transistor for a low voltage having a comparatively thin gate oxide film and a MIS type transistor for high voltage with a comparatively thick gate oxide films are formed around the memory transistor.Abstract:
A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.read more
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References
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Patent
Semiconductor integrated circuit device with memory MISFETS and thin and thick gate insulator MISFETS
TL;DR: A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS-type transistor for a low voltage having a comparatively thin gate oxide film and a MIS type transistor for high voltage with a comparatively thick gate oxide films are formed around the memory transistor as mentioned in this paper.
Patent
Nonvolatile static random access memory devices
TL;DR: In this article, a nonvolatile, semiconductor random access memory cells comprising a static, RAM cell and a non-volatile memory element which may be interconnected with the static random-access memory cell by capacitative coupling is proposed.
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Method of making a plurality of MOSFETs having different threshold voltages
TL;DR: In this article, an integrated circuit using MOSFETs having varying threshold voltages permitting improved performance and reduced area utilization on a monolithic semiconductor chip is produced by selectively varying ion implantation doses in the channels of the MOSFLETs.
Patent
Method for preparing complementary semiconductor device
TL;DR: In this article, the gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type.
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