Open AccessProceedings Article
FPGA implementation of parallel digital image processor
Przemyslaw Brylski,Michal Strzelecki +1 more
- pp 25-28
TLDR
The architecture and algorithm modifications presented in this paper are aimed to reduction the FPGA resources, namely the area of the image pixel that represents basic image processing unit.Abstract:
This paper describes a FPGA implementation of the parallel digital image processor for an image segmentation and other analysis like edge detection or noise removal. The architecture and algorithm modifications presented in this paper are aimed to reduction the FPGA resources, namely the area of the image pixel that represents basic image processing unit.read more
Citations
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Optimization of the FPGA parallel image processor
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Parallel digital image processor implemented in FPGA technology
TL;DR: A hardware implementation of parallel digital image processor in FPGA technology with 16×16 array for image processing and analysis is presented and results are presented and discussed.
References
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Book
Circuit Design with VHDL
TL;DR: This book's highly original approach of teaching through extensive system examples as well as its unique integration of VHDL and design make it suitable both for use by students in computer science and electrical engineering.
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VHDL for Programmable Logic
TL;DR: This chapter discusses VHDL, CPLDs, and FPGAs, as well as Hierarchy in Large Designs, and several approaches to Writing Test Benches, including overloaded Read and Write Procedures.
Proceedings Article
The architecture of a digital network for image analysis
TL;DR: In this article, the authors describe a new architecture for a parallel, digital image processor which performs several image processing tasks like segmentation, edge detection and noise removal, which is aimed for reduction the FPGA area of a pixel, which represents basic image processing unit.