Proceedings ArticleDOI
Frame buffer energy optimization by pixel prediction
Kimish Patel,Enrico Macii,Massimo Poncino +2 more
- pp 98-101
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TLDR
The proposed architecture allows to dynamically update the locality information, and, unlike previous approaches, it works virtually independent of the size and position of the updates of the display frames.Abstract:
We propose a technique to reduce the energy consumption of the frame buffer memory, based on the spatial locality of images and display frames. Our scheme reduces energy by selectively avoiding reads from the frame buffer when identical adjacent pixels are detected. This is made possible by using an auxiliary memory that stores the locality information. The proposed architecture allows to dynamically update the locality information, and, unlike previous approaches, it works virtually independent of the size and position of the updates of the display frames. Experimental results evaluated on a set of typical graphical applications show a reduction of about 40% of frame buffer reads.read more
Citations
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Patent
Graphics processing systems
Ja Rn Nystad,Rune Holm +1 more
TL;DR: In this article, a graphics processing system includes a graphics processor and a memory for storing data to be used by and generated by the graphics processor, which is used in a subsequent rendering pass.
Patent
Graphics processing system
TL;DR: In this paper, a bounding volume representation of a complex object made up of many individual primitives is generated and the scene is then processed using the bounding volumes in place of the actual primitives making up the complex object.
Patent
Methods of and apparatus for controlling the reading of arrays of data from memory
TL;DR: In this article, a display controller uses similarity meta-data associated with the output frame in the frame buffer to determine whether a new block of data to be processed for display is similar to a block of stored in the local memory of the display controller or not.
Proceedings ArticleDOI
Improving energy efficiency for mobile platforms by exploiting low-power sleep states
TL;DR: A novel framework, called E2S3 (Energy Efficient Sleep-State Selection), that dynamically enters the optimal low-power sleep state to minimize the system power consumption and significantly reduces the platform energy consumption, without compromising system performance.
Proceedings ArticleDOI
GemDroid: a framework to evaluate mobile platforms
Nachiappan Chidambaram Nachiappan,Praveen Yedlapalli,Niranjan Soundararajan,Mahmut Kandemir,Anand Sivasubramaniam,Chita R. Das +5 more
TL;DR: GemDroid is designed by integrating the Android open-source emulator for facilitating execution of mobile applications, the GEM5 core simulator for analyzing the CPU and memory centric designs, and models for several IPs to collectively study their impact on system-level performance and power.
References
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Journal Article
A survey of design techniques for system-level dynamic power management : Special section on low-power electronics and design
TL;DR: Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components as mentioned in this paper.
Journal ArticleDOI
A survey of design techniques for system-level dynamic power management
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Proceedings ArticleDOI
Low-power color TFT LCD display for hand-held embedded systems
TL;DR: An LCD (Liquid Crystal Display) is a standard display device for hand-held embedded systems that is composed of an LCD panel, a frame buffer memory, an LCD and frame buffer controller, and a backlight inverter and lamp.
Journal ArticleDOI
A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM
Masahiko Yoshimoto,K. Anami,H. Shinohara,T. Yoshihara,H. Takagi,S. Nagao,S. Kayano,T. Nakano +7 more
TL;DR: This paper describes a divided word-line (DWL) structure which solves inherent problems encountered in VLSI static RAMs and to select it hierarchically with little area penalty using conventional process technology.
Proceedings ArticleDOI
Optimizing the DRAM refresh count for merged DRAM/logic LSIs
TL;DR: In merged DRAM/logic LSIs, the DRAM portion could suffer from shorter data retention time because of heat and noise caused by the logic portion, so several DRAM refresh architectures are proposed to eliminate unnecessary DRAM refreshes.