Proceedings ArticleDOI
Generalized algorithm of building summation codes for the tasks of technical diagnostics of discrete systems
Dmitry Efanov,Valery Sapozhnikov,Vladimir Sapozhnikov +2 more
- pp 1-7
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TLDR
A detailed analysis of error controlled divisible codes' building techniques was carried out, aimed at error detection in data vectors, which relate to summation codes' class, making it possible to broaden the selection field of encoding variant in the process of reliable discrete systems' synthesis.Abstract:
A detailed analysis of error controlled divisible codes' building techniques was carried out, aimed at error detection in data vectors, which relate to summation codes' class. Summation codes classification was suggested, covering the whole diversity of modification methods of the existing classical and modular summation codes. New methods of summation codes modification were specified making it possible to build codes with different characteristics. A universal algorithm of building poly-modulus summation code was developed, capturing all the existing building techniques of summation codes. An algorithm of selecting a building technique of a code was developed, when organizing a concurrent error-detection (CED) system of a logical unit with the given topology. The presented results make it possible to broaden the selection field of encoding variant in the process of reliable discrete systems' synthesis.read more
Citations
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Proceedings ArticleDOI
Ternary Parity Codes: Features
TL;DR: It is proved that the described ternary parity code, built based on using a single convolution function modulo three, has the data vectors uniform distribution property between check single-trit vectors.
Journal ArticleDOI
The Synthesis Conditions of Completely Self-Testing Embedded-Control Circuits Based on the Boolean Complement Method to the “1-out-of- m ” Constant-Weight Code
TL;DR: A synthesis method based on the Boolean complement to the “1-out-of-m” constant-weight code is proposed for completely self-checking circuits of embedded control of combinational logic devices.
Boolean complement method for combinational circuits testing using binary separable codes
TL;DR: The conditions for the use of binary separable codes for their use in the concurrent error-detection systems organization according to the method of logical addition are established.
References
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TL;DR: Some new codes are described which are separable and are perfect error detection codes in a completely asymmetric channel and the new code is found to compare favorably in error detection capability in several cases.
Proceedings ArticleDOI
Which concurrent error detection scheme to choose
TL;DR: Simulation results indicate that, for the simulated combinational logic circuits, although diverse duplex systems (with two different implementations of the same logic function) sometimes have marginally higher area overhead, they provide significant protection against multiple failures and CMFs compared to other CED techniques like parity prediction.
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TL;DR: As the author effectively demonstrates, matrix codes are far more flexible than polynomial codes, as they are capable of expressing various types of code functions.
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TL;DR: This chapter discusses codes for High-Speed Memories I: Bit Error Control Codes, which consist of single-Byte Error Correcting and Double-Bit Error Detecting, as well as application of the UEC / UEP Codes.
Journal ArticleDOI
Synthesis of circuits with low-cost concurrent error detection based on Bose-Lin codes
D. Das,Nur A. Touba +1 more
TL;DR: An efficient scheme for concurrent error detection in sequential circuits with no constraint on the state encoding is presented and its cost is reduced significantly compared to other methods based on other codes.