Proceedings ArticleDOI
H-Saber: An FPGA-Optimized Version for Designing Fast and Efficient Post-Quantum Cryptography Hardware Accelerators
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In this paper , the authors proposed a version of Saber's code optimized for FPGA targets, which showed how they detected and improved the performance of the reference code, achieving competitive results compared to the hand-made RTL-based designs.Abstract:
With the performance promises of quantum computers, standard encryption algorithms can be defeated. For this reason, a set of new quantum-resistant algorithms have been proposed and submitted for a standardization contest initiated by NIST. While the submission requirement was ANSI C for the reference implementation, NIST encouraged providing software implementations optimized for different target platforms, such as high-performance CPUs, embedded microcontrollers, and FPGAs. Yet, none of the algorithms submitted any FPGA-optimized code, due to the large and expensive development time required for coding at RTL. High-Level synthesis (HLS) covers the gap by creating automatically hardware code for FPGA out of C/C++. However, the quality of results is suboptimal due to the limitation imposed by the inadequacy of source code for HLS. In this paper, we propose a version of Saber’s code optimized for FPGA targets. We show how we detected and improved the performance of the reference code, achieving competitive results compared to the hand-made RTL-based designs.read more
References
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Journal ArticleDOI
High-Level Synthesis for FPGAs: From Prototyping to Deployment
TL;DR: AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx are used as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains.
Journal ArticleDOI
Are We There Yet? A Study on the State of High-Level Synthesis
TL;DR: HLS is currently a viable option for fast prototyping and for designs with short time to market and to help close the QoR gap, a survey of literature focused on improving HLS concludes.
Proceedings ArticleDOI
Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels
TL;DR: A comprehensive benchmark of the run-time performance and energy efficiency of a wide range of vision kernels is conducted and rationales for why a given underlying hardware architecture innately performs well or poorly based on the characteristics of arange of vision kernel categories are discussed.
Journal ArticleDOI
Transformations of High-Level Synthesis Codes for High-Performance Computing
TL;DR: A collection of optimizing transformations for HLS, targeting scalable and efficient architectures for high-performance computing (HPC) applications, is presented, aiming to establish a common toolbox to guide both performance engineers and compiler engineers in tapping into the performance potential offered by spatial computing architectures using HLS.
Journal ArticleDOI
High-speed Instruction-set Coprocessor for Lattice-based Key Encapsulation Mechanism: Saber in Hardware
Sujoy Sinha Roy,Andrea Basso +1 more
TL;DR: For the module dimension 3, the coprocessor computes CCA key generation, encapsulation, and decapsulation in only 5,453, 6,618 and 8,034 cycles respectively, making it the fastest hardware implementation of Saber to the authors' knowledge.