Patent
High-voltage vertical power component
Samuel Menard,Gaël Gautier +1 more
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TLDR
In this article, a vertical power component including a silicon substrate of a first conductivity type, a lower surface of the substrate supporting a single electrode, and an upper region of the second conductivity Type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.Abstract:
A vertical power component including: a silicon substrate of a first conductivity type; on the side of a lower surface of the substrate supporting a single electrode, a lower layer of the second conductivity type; and on the side of an upper surface of the substrate supporting a conduction electrode and a gate electrode, an upper region of the second conductivity type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.read more
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Patent
Integrated Circuit Device Having Through-Silicon-Via Structure and Method of Manufacturing the Same
TL;DR: In this paper, an integrated circuit device including a through-silicon-via (TSV) structure and methods of manufacturing the same are provided, which may include the TSV structure penetrating through a semiconductor structure.
Patent
Vertical power component
Samuel Menard,Gaël Gautier +1 more
TL;DR: In this article, a highvoltage vertical power component including a silicon substrate of a first conductivity type and a first semiconductor layer of the second conductivity types extending into the silicon substrate from an upper surface of the substrate, where the component periphery includes: a porous silicon ring extending into a substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the first conductivities type, extending from a lower surface of a silicon surface to the polysilicon ring.
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Integrated circuit device having through-silicon-via structure
TL;DR: In this paper, an integrated circuit device including a through-silicon-via (TSV) structure and methods of manufacturing the same are provided, which may include the TSV structure penetrating through a semiconductor structure.
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Yannick Hague,Samuel Menard +1 more
TL;DR: In this article, the authors describe a bi-directional power switch having first (TFA) and second (TH) connected thyristors in anti-parallel between the first (A1) and the second (A2) of the switch conduction terminals.
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TL;DR: In this paper, a power switching device may include a semiconductor substrate and a body region comprising an n-type dopant, the body region disposed in an inner portion of the semiconducting substrate; a first base layer disposed adjacent a first surface of the substrate, the first p-base layer comprising a p-type op-drug, the second base layer comprising p-drone, and a second field stop layer arranged between the first base and the body regions.
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Thyristor and method of manufacture
TL;DR: In this article, a semiconductor substrate with first and second major surfaces has been proposed, where the first major surface has a vertical boundary that has a notched portion and the second major surface extends from the first surface into the second surface.
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Composant de puissance vertical
TL;DR: In this paper, the authors concerne un composant de puissance vertical comportant : un substrat (1) en silicium dope d'un premier type de conductivite ; un caisson localise (3) du second type of conductivité s'etendant depuis une face superieure du substrat ; and du cote de la face superiesure du substrateat (2), a structure de passivation revetant, sur et en contact avec ladite region peripherique de substrat, une premiere region
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CMOS Device for Reducing Charge Sharing Effect and Fabrication Method Thereof
TL;DR: In this article, a CMOS device of reducing charge sharing effect and a fabrication method of fabrication is presented, where the defect states in the porous silicon trap carriers and the formation of a shallow trench isolation (STI) region and a isolation region underneath only needs one time photolithography.