Open AccessDOI
Implementation of Custom Precision Floating Point Arithmetic on FPGAs
TLDR
This paper has described and evaluated the performance of custom-precision, pipelined, floating point arithmetic core for the conversion to and from signed binary numbers and assessed the practical implications of using these algorithms on the Xilinx Spartan 3E FPGA boards.Abstract:
Floating point arithmetic is a common requirement in signal processing, image processing and real time data acquisition & processing algorithms. Implementation of such algorithms on FPGA requires an efficient implementation of floating point arithmetic core as an initial process. We have presented an empirical result of the implementation of custom-precision floating point numbers on an FPGA processor using the rules of IEEE standards defined for single and double precision floating point numbers. Floating point operations are difficult to implement on FPGAs because of their complexity in calculations and their hardware utilization for such calculations. In this paper, we have described and evaluated the performance of custom-precision, pipelined, floating point arithmetic core for the conversion to and from signed binary numbers. Then, we have assessed the practical implications of using these algorithms on the Xilinx Spartan 3E FPGA boards.read more
Citations
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Proceedings ArticleDOI
Custom Precision Method of Floating-Point Operations of FFT Processing for Optimized Area and Delay Performance
TL;DR: In this article , an approach of custom precision of 12-bit has been proposed for the FFT implementation for hardware design, which has been successfully verified for better results of reduced delay of 8.191ns with the reduced number of LUTs of 3149.
Journal ArticleDOI
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DFM Assisted Scan Data Diagnostic Analysis For Fast Systematic Defect Determination
Colin Hui,Jianhao Zhu,Thomas Berndt,Thomas Herrmann,Karthik Nataraj Krishnamoorthy,Valerio Perez,Yeo Sky +6 more
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Hold Time Improvement with Dynamic Dual Power Zone and Useful Active Load Technique On Sequential Cell
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References
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StandardDOI
IEEE Standard for Floating-Point Arithmetic
Dan Zuras,M. F. Cowlishaw,Alex Aiken,Matthew Applegate,David H. Bailey,Steve Bass,Dileep Bhandarkar,Mahesh Bhat,David Bindel,Sylvie Boldo,Stephen Canon,Steven R. Carlough,Marius Cornea,John H. Crawford,Joseph D. Darcy,Debjit Das Sarma,Marc Daumas,Bob Davis,Mark Davis,Dick Delp,James Demmel,Mark A. Erle,Hossam A. H. Fahmy,J. P. Fasano,Richard J. Fateman,Eric Feng,Warren E. Ferguson,Alex Fit-Florea,Laurent Fournier,Chip Freitag,Ivan Godard,Roger A. Golliver,David Gustafson,Michel Hack,John R. Harrison,John Hauser,Yozo Hida,Chris N. Hinds,Graydon Hoare,David G. Hough,Jerry Huck,Jim Hull,Michael Ingrassia,David V. James,Rick James,William Kahan,John Kapernick,Richard Karpinski,Jeff Kidder,Plamen Koev,Ren-Cang Li,Zhishun A. Liu,Raymond Mak,Peter Markstein,David W. Matula,Guillaume Melquiond,Nobuyoshi Mori,Ricardo Morin,Ned Nedialkov,Craig Nelson,Stuart Oberman,Jon Okada,Ian Ollmann,Michael Parks,Tom Pittman,Eric Postpischil,Jason Riedy,Eric M. Schwarz,David Scott,Don Senzig,Ilya Sharapov,Jim Shearer,Michael Siu,Ron Smith,Chuck Stevens,Peter Tang,Pamela J. Taylor,James W. Thomas,Brandon Thompson,Wendy Thrash,Neil Toda,Son Dao Trong,Leonard Tsai,Charles Tsen,Fred Tydeman,Liang Wang,Scott Westbrook,Steve Winkler,Anthony Wood,Umit Yalcinalp,Fred Zemke,Paul Zimmermann +91 more
Proceedings ArticleDOI
A re-evaluation of the practicality of floating-point operations on FPGAs
TL;DR: The implementation of IEEE single precision floating-point multiplication and addition is discussed, followed by a discussion of an algorithm, matrix multiplication, based on these operations, which achieves performance comparable to conventional microprocessors.
Proceedings ArticleDOI
Implementation of IEEE single precision floating point addition and multiplication on FPGAs
TL;DR: This work has explored FPGA implementations of addition and multiplication for IEEE single precision floating-point numbers, and prototypes have been implemented on Altera FLEX8000s, and peak rates of 7 MFlops for 32-bit addition and 2.3 M flop multiplication have been obtained.
Proceedings ArticleDOI
An efficient implementation of floating point multiplier
TL;DR: An efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA using VHDL to implement a technology-independent pipelined design.
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