Proceedings ArticleDOI
Implementation of non-linear pipelined floating point adder
P Dipu,Naveen S Hampannavar,P. Jayakrishnan +2 more
- pp 257-259
TLDR
This paper has used non-linear pipelining concept to divide the adder operation into multiple sub-functional units, which complete their execution in variable time and are dynamically scheduled.Abstract:
Floating point addition is a frequently used operation in real time applications and image processing. Its structure is complex due to multiple shifts, addition and normalization units which increase the latency of operation. In order to have the high performance low latency is desired along with higher throughput. In this paper we have used non-linear pipelining concept to divide the adder operation into multiple sub-functional units. The functional units complete their execution in variable time and are dynamically scheduled. This also leads to hardware reutilization. Floating point numbers will be considered in their IEEE754 half precision format [16 bits]: 1bit sign, 5 bit exponent, 10 bit mantissa. The architecture is developed with Verilog HDL and simulated using ALTERA Device EP2C20F484C7.read more
References
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Book
Advanced Computer Architecture: Parallelism,Scalability,Programmability
TL;DR: This book deals with advanced computer architecture and parallel programming techniques and is suitable for use as a textbook in a one-semester graduate or senior course, offered by Computer Science, Computer Engineering, Electrical Engineering, or Industrial Engineering programs.
Latency and throughput tradeoffs in self-timed speed-independent pipelines and rings
TL;DR: This report demonstrates the utility of a graph-based methodology for analyzing the timing dependencies and uses it to make comparisons of different configurations and shows that the extremes for high throughput and low latency differ significantly.
Journal ArticleDOI
Fast, Efficient Floating-Point Adders and Multipliers for FPGAs
TL;DR: The designs presented here enable a Xilinx Virtex4 FPGA to achieve 270 MHz IEEE compliant double precision floating-point performance with a 9-stage adder pipeline and 14-stage multiplier pipeline.
Proceedings ArticleDOI
FPGA based implementation of a double precision IEEE floating-point adder
TL;DR: The proposed double precision IEEE floating-point adder has been implemented with XC2V6000 and XC3S1500 Xilinx© FPGA devices and exhibited improvement in the latency and also in the operational chip area management.