Patent
Integrated bipolar-CMOS circuit isolation for providing different backgate and substrate bias
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TLDR
In this paper, a bipolar-CMOS circuit with a NMOS transistor site (18) electrically isolated from a bipolar transistor well (26) by a deep diffusion ring is described.Abstract:
Disclosed is a bipolar-CMOS circuit which includes a NMOS transistor site (18) electrically isolated from a bipolar transistor site (16). The NMOS transistor site (18) includes a semiconductor region (24) isolated from a bipolar transistor well (26) by deep diffusion ring (32). A buried layer (13) forms a bottom of the deep diffusion isolation ring (32). A backgate voltage can be applied to the isolated semiconductor region (24) of the NMOS device, which bias may be different than that applied to the substrate (10). Optimum performance of the NMOS transistor is thus assured irrespective of the magnitude of operating voltage of the bipolar transistor.read more
Citations
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References
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