Patent
Master latch circuit with signal level displacement for a dynamic flip-flop
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TLDR
In this article, a master latch circuit with signal level displacement for a flip-flop clocked by a clock pulse signal (Clk) is presented, where the data signal controls only transistors of a single type (either only N-channel or only P-channel).Abstract:
A master latch circuit (10) with signal level displacement for a flip-flop (1) clocked by a clock pulse signal (Clk), wherein the master latch circuit (10) comprises a signal delay circuit (13) which delays and inverts the clock pulse signal (ClK), resulting in a specific time delay (AT), and a circuit node (14) which, in a charging phase wherein the clock pulse signal (Clk) is logically low, is charged to an operational voltage (VB) and which, in an evaluation phase when the clock pulse signal (Clk) and delayed, inverted clock pulse signal (ClkDELAY) are logically high, is discharged according to a specific data signal (D), wherein the data signal controls only transistors of a single type (either only N-channel or only P-channel). The master latch circuit (10) has only one supply voltage .read more
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References
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Patent
Temperature sensor and method for operating a temperature sensor
Karl Schrödinger,Jaro Stimma +1 more
TL;DR: In this paper, a temperature sensor has a first FET transistor circuit and a second transistor circuit, and both circuits are operated at an operating point that lies outside the temperature independent operating point.
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Patent
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Patent
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