Patent
Match line control circuit for content addressable memory
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TLDR
In this paper, a match line control circuit includes a weak, static pull-up transistor and a strong, dynamic pullup transistor coupled between the match line of an associated CAM and a supply voltage.Abstract:
A match line control circuit includes a weak, static pull-up transistor and a strong, dynamic pull-up transistor coupled between a match line of an associated CAM and a supply voltage. Prior to compare operations, both the static pull-up transistor and the dynamic pull-up transistor are in a conductive state and thereby quickly charge the match line to the supply voltage. During compare operations, the dynamic transistor is turned off to reduce current flow between the supply voltage and the match line. In some embodiments, the static pull-up transistor and the dynamic pull-up transistor are configured to match the parasitics of the CAM cells 10 coupled to the match line, thereby increasing performance of the associated CAM.read more
Citations
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Patent
Content addressable memory with programmable word width and programmable priority
Bindiganavale S. Nataraj,Nilesh A. Gharia,Rupesh R. Roy,Jose P. Pereira,Varadarajan Srinivasan,Sandeep Khanna,Hok F. Wong +6 more
TL;DR: In this paper, a content addressable memory (CAM) device including a CAM array and a priority index table is presented, where each CAM array has a plurality of rows of CAM cells, each row including a number of row segments and being adapted to store a data word that spans a selectable number of the row segments.
Patent
Selective match line pre-charging in a partitioned content addressable memory array
TL;DR: In this paper, rows of a CAM array are partitioned into first and second row segments, and a first match line segment is pre-charged to enable detection of match conditions within the associated first row segment.
Patent
Content addressable memory with block-programmable mask write mode, word width and priority
Bindiganavale S. Nataraj,Nilesh A. Gharia,Rupesh R. Roy,Jose Pio Pereira,Varadarajan Srinivasan,Sandeep Khanna,Hok F. Wong +6 more
TL;DR: In this article, a content addressable memory (CAM) device consisting of a plurality of CAM blocks and a block control circuit is presented. But the authors do not consider the performance of the CAM blocks.
Patent
Static content addressable memory cell
TL;DR: In this article, the authors propose a static content addressable memory (CAM) cell with complementary data nodes capacitively coupled to ground, first and second access transistors, each coupled between a data node of the latch and a respective data line.
Patent
Inter-row configurability of content addressable memory
TL;DR: A CAM system for storing a data word chain having a sequence of one or more data words stored in a row of CAM cells is described in this article, where the control signals are generated by an instruction decoder in response to decoding separate instructions for comparing the first data word, a continuing data word and the last data word.
References
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Patent
Content-addressable-memory control circuit
TL;DR: In this article, a comparison operation is done in a content addressable memory cell, and an N-MOSFET is switched on or off according to the result of comparison, and the control signal SR goes to a logic high level.
Patent
Fast content addressable memory with reduced power consumption
TL;DR: In this paper, a content addressable memory with a COMPARE circuit was proposed. But the COMPARE function was performed without loading the first and second bit lines of the memory.
Patent
Method of using associative memories and an associative memory
TL;DR: In this paper, a retrieval is performed using reference data applied from an exterior and the pair of attribute and data stored in each word memory of associative memories, and a signal representing a match or mismatch of both attributes and data except the attribute is supplied to a data line.