Proceedings ArticleDOI
Memory consistency and event ordering in scalable shared-memory multiprocessors
Kourosh Gharachorloo,Daniel E. Lenoski,James Laudon,Phillip B. Gibbons,Anoop Gupta,John L. Hennessy +5 more
- Vol. 18, pp 15-26
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TLDR
A new model of memory consistency, called release consistency, that allows for more buffering and pipelining than previously proposed models is introduced and is shown to be equivalent to the sequential consistency model for parallel programs with sufficient synchronization.Citations
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Review: A survey on security issues in service delivery models of cloud computing
S. Subashini,V. Kavitha +1 more
TL;DR: A survey of the different security risks that pose a threat to the cloud is presented and a new model targeting at improving features of an existing model must not risk or threaten other important features of the current model.
Proceedings ArticleDOI
Transactional memory: architectural support for lock-free data structures
Maurice Herlihy,J. Eliot B. Moss +1 more
TL;DR: Simulation results show that transactional memory matches or outperforms the best known locking techniques for simple benchmarks, even in the absence of priority inversion, convoying, and deadlock.
Journal ArticleDOI
A survey and comparison of peer-to-peer overlay network schemes
TL;DR: A survey and comparison of various Structured and Unstructured P2P overlay networks is presented, categorize the various schemes into these two groups in the design spectrum, and discusses the application-level network performance of each group.
Book
Parallel Computer Architecture: A Hardware/Software Approach
TL;DR: This book explains the forces behind this convergence of shared-memory, message-passing, data parallel, and data-driven computing architectures and provides comprehensive discussions of parallel programming for high performance and of workload-driven evaluation, based on understanding hardware-software interactions.
Journal ArticleDOI
Shared memory consistency models: a tutorial
TL;DR: This work describes an alternative, programmer-centric view of relaxed consistency models that describes them in terms of program behavior, not system optimizations, and most of these models emphasize the system optimizations they support.
References
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Journal ArticleDOI
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
TL;DR: Many large sequential computers execute operations in a different order than is specified by the program, and a correct execution by each processor does not guarantee the correct execution of the entire program.
Journal ArticleDOI
Shared memory consistency models: a tutorial
TL;DR: This work describes an alternative, programmer-centric view of relaxed consistency models that describes them in terms of program behavior, not system optimizations, and most of these models emphasize the system optimizations they support.
Journal ArticleDOI
The directory-based cache coherence protocol for the DASH multiprocessor
TL;DR: The design of the DASH coherence protocol is presented and how it addresses the issues of correctness, performance and protocol complexity are discussed and compared to the IEEE Scalable Coherent Interface protocol.
Proceedings Article
The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture.
Gregory Francis Pfister,William C. Brantley,David A. George,Steve L. Harvey,Wally J. Kleinfelder,Kevin P. McAuliffe,Evelin S. Melton,V. Alan Norton,Jodi Weiss +8 more
Book
Efficient and Correct Execution of Parallel Programs That Share Memory
Dennis Shasha,Marc Snir +1 more
TL;DR: The analysis finds a minimal set of delays that enforces sequential consistency in the execution of parallel programs on shared-memory multiple-instruction-stream, multiple-data-stream (MIMD) computers and uses a conflict graph similar to that used to schedule transactions in distributed databases to do without locks.