Patent
Method and apparatus for designing circuits for wave pipelining
Ramalingam Sridhar,Xuguang Zhang +1 more
TLDR
In this paper, a family of CFET logic circuits useful for wave-pipeline systems is described, and a method to design the same is presented. And, NAND, OR, NOR, XOR, XNOR, select, select-invert, invert, and notinvert functions.Abstract:
A family of CFET logic circuits useful for wave-pipeline systems is described, and a method to design same. The invention uses complementary transmission gates and pull-up or pull-down transistors to achieve a family of CFET logic circuits which include AND, NAND, OR, NOR, XOR, XNOR, select, select-invert, invert, and not-invert functions. Each circuit is tuned to provide substantially equal delays, high-quality ones and zeros, and substantially equal rise and fall times, for every combination of input-state transition and output-state transition.read more
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Patent
Power converter circuitry and method
Kent Kernahan,John Carl Thomas +1 more
TL;DR: In this article, a control system and method for simultaneously regulating the operation of a plurality of different types of switching power converters is presented, where the system utilizes in regulating the sampled data and nonlinear feedback control loops.
Patent
Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having Equal Number of PMOS and NMOS Transistors
TL;DR: In this article, a gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction, each of which is fabricated from a respective originating rectangular-shaped layout feature.
Patent
Methods for Defining Dynamic Array Section with Manufacturing Assurance Halo and Apparatus Implementing the Same
TL;DR: In this paper, a method for defining a dynamic array section to be manufactured on a semiconductor chip is described, which includes defining a peripheral boundary of the dynamic array and a manufacturing assurance halo outside the boundary.
Patent
Methods for designing standard cell transistor structures
TL;DR: In this paper, a transistor model for a P-type and an N-type transistor of a CMOS standard cell is defined, and the optimization is performed by substantially minimizing an average delay for the transistor structure.
Patent
Methods for defining contact grid in dynamic array architecture
TL;DR: In this article, the vertical connection structures are placed at a number of gridpoints within a vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels.
References
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Graph-Based Algorithms for Boolean Function Manipulation
TL;DR: In this paper, the authors present a data structure for representing Boolean functions and an associated set of manipulation algorithms, which have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large.
Journal ArticleDOI
Binary Decision Diagrams
TL;DR: This paper describes a method for defining, analyzing, testing, and implementing large digital functions by means of a binary decision diagram that provides a complete, concise, "implementation-free" description of the digital functions involved.
Book
Principles of CMOS VLSI Design: A Systems Perspective
Neil Weste,K Eshraghian +1 more
TL;DR: CMOS Circuit and Logic Design: The Complemenatry CMOS Inverter-DC Characteristics and Design Strategies.
Journal ArticleDOI
A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic
Kazuo Yano,Toshiaki Yamanaka,Takashi Nishida,M. Saito,Katsuhiro Shimohigashi,Akihiro Shimizu +5 more
TL;DR: In this article, a complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path, which consists of complementary inputs/outputs, an nMOS pass transistor logic network, and CMOS output inverters, and is twice as fast as conventional CMOS due to lower input capacitance and high logic functionality.
Journal ArticleDOI
The IBM system/360 model 91: floating-point execution unit
TL;DR: The principal requirement for the Model 91 floating-point execution unit was that it be designed to support the instructionissuing rate of the processor, so separate, instruction-oriented algorithms for the add, multiply, and divide functions were developed.