Patent
Method and apparatus for facilitating instruction processing of a digital computer
TLDR
In this paper, the authors propose to use a cache memory and a main memory with a transformation unit between the main memory and the cache memory so that at least a portion of an information unit retrieved from the cache may be transformed during retrieval of the information (fetch) from a mainmemory and prior to storage in the cache (cache).Abstract:
A computer having a cache memory and a main memory is provided with a transformation unit between the main memory and the cache memory so that at least a portion of an information unit retrieved from the main memory may be transformed during retrieval of the information (fetch) from a main memory and prior to storage in the cache memory (cache). In a specific embodiment, an instruction may be predecoded prior to storage in the cache memory. In another embodiment involving a branch instruction, the address of the target of the branch is calculated prior to storing in the instruction cache. The invention has advantages where a particular instruction is repetitively executed since a needed decode operation which has been partially performed previously need not be repeated with each execution of an instruction. Consequently, the latency time of each machine cycle may be reduced, and the overall efficiency of the computing system can be improved. If the architecture defines delayed branch instructions, such branch instructions may be executed in effectively zero machine cycles. This requires a wider bus and an additional register in the processor to allow the fetching of two instructions from the cache memory in the same cycle.read more
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Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
TL;DR: The branch prediction cache (BPC) as mentioned in this paper provides a tag identifying the address of instructions causing a branch, a record of the target address which was branched to on the last occurrence of each branch instruction, and a copy of the first several instructions beginning at this target address.
Patent
Decoding guest instruction to directly access emulation routines that emulate the guest instructions
TL;DR: In this article, a system for decoding guest instructions includes an emulation routine store in host processor addressable memory having a set of emulation programs beginning at corresponding emulation program addresses, and logic is provided which retrieves a current guest instruction in the sequence and jumps directly to an emulation program address in response to the current instruction.
Patent
Two-level branch prediction cache
TL;DR: An improved branch prediction cache (BPC) as mentioned in this paper utilizes a hybrid cache structure that provides two levels of branch information caching, a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions.
Patent
Apparatus for executing programs for a first computer architechture on a computer of a second architechture
TL;DR: In this paper, the authors propose a set of entry exceptions, called entry exception, exit exception, entry handler, and resumption exception, which are cooperatively designed to maintain an association between a thread and an extended context of the thread through context change induced by the operating system.
Patent
Programmable data encryption engine for advanced encryption standard algorithm
Yosef Stein,Haim Primo +1 more
TL;DR: In this article, a programmable data encryption engine for performing the cipher function of an AES algorithm includes a parallel look-up table system responsive in a first mode to a first data block for implementing an AES selection function and executing the multiplicative inverse in GF -1 ( 2 8 ) and applying an affine over GF( 2 ) transformation to obtain a sub-byte transformation and in a second mode to the subbyte transformation to transform the sub-transformer to get a shift row transformation.
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Patent
Cache memory architecture with decoding
TL;DR: In this article, it is assumed that an information processing unit and storage system comprising at least one low speed, high capacity main memory having relatively long access time and including a plurality of data pages stored therein and at least a high speed, low capacity cache memory having a relatively short access time adapted to store a predetermined plurality of subsets of the information stored in said main memory data pages.
Patent
Instruction buffer associated with a cache memory unit
TL;DR: In this article, an improved instruction buffer associated with a cache memory unit is proposed to store data groups to which transfer, either conditional or unconditional, has been identified in the sequence currently being executed.