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Method and apparatus for generating a variable capacitance for synthesizing high-frequency signals for wireless communications

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TLDR
In this article, a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) was proposed to synthesize high-frequency signals, such as wireless communication signals.
Abstract
A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. The continuously variable capacitance may be formed by using a plurality of separate capacitance circuits. The individual capacitance circuits may include two capacitors coupled to a variable resistance element. The variable resistance element may be a transistor controlled by an analog control voltage. The total capacitance of the continuously variable capacitance may be substantially linear with respect to the phase of the VCO output while the individual capacitance circuits exhibit nonlinear behavior.

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References
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A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-/spl mu/m CMOS

TL;DR: In this article, a dual-modulus divide-by-128/129 prescaler was developed in a 0.7-/spl mu/m CMOS technology, which enables the limitation of the high-speed section of the precaler to only one divideby-two flipflop.
Journal ArticleDOI

A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler

TL;DR: In this article, the implementation of two high-frequency building blocks for low-phase-noise 1.8 GHz PLL in a standard 0.7/spl mu/m CMOS process is discussed.
Journal ArticleDOI

A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops

TL;DR: In this paper, a 1.2 GHz dual-modulus prescaler IC fabricated with 0.8 /spl mu/m CMOS technology is presented, which includes a synchronous counter and an asynchronous counter.
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Multiaccumulator sigma-delta fractional-n synthesis

TL;DR: In this article, a fractional-N synthesizer employing at least a second order sigma-delta modulator is described, where the most significant bits from the output accumulator (1011) are used as the carry out control for the variable divisor of the loop divider (103).
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Frequency synthesizer with fractional division ratio and jitter compensation

TL;DR: In this article, a frequency synthesizer with good resolution is obtained by a unity increase of the dividing ratio for a controlled proportion of the reference frequency cycles thus giving a fractional dividing ratio.