Patent
Method and apparatus for rapidly switching processes in a computer system
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TLDR
In this paper, an apparatus and method for switching the context of state elements of a very fast processor within a clock cycle when a cache miss occurs is presented, which is particularly useful for minimizing the average instruction cycle time for a processor with a main memory access time exceeding 15 processor clock cycles.Abstract:
An apparatus and method are disclosed for switching the context of state elements of a very fast processor within a clock cycle when a cache miss occurs. To date, processors either stay idle or execute instructions out of order when they encounter cache misses. As the speed of processors become faster, the penalty for a cache miss is heavier. Having multiple copies of state elements on the processor and coupling them to a multiplexer permits the processor to save the context of the current instructions and resume executing new instructions within one clock cycle. The invention disclosed is particularly useful for minimizing the average instruction cycle time for a processor with a main memory access time exceeding 15 processor clock cycles. It is understood that the number of processes who's states are duplicated may easily be a large number n.read more
Citations
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Altering thread priorities in a multithreaded processor
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References
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Patent
Partitioned cache memory with partition look-aside table (PLAT) for early partition assignment identification
TL;DR: Partition Look-Aside Table (PLAT) as discussed by the authors is a cache partition identifier, a control field, and a congruence-class address for locating associated data in the identified partition.
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Concurrent task and instruction processor and method
TL;DR: In this paper, a processor for concurrent processing of tasks and instructions is described, which is basically a multiple instruction, multiple data stream (MIMD) digital computer that utilizes pipelining for control and function units but avoids precedence constraint penalties.
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Gigy Baror,Brian Case,Rod Fleck,Philip M. Freidin,Smeeta Gupta,William M. Johnson,Cheng-Gang Kong,Ole Moller,Timothy Alan Olson,David I. Sorensen +9 more
TL;DR: In this article, a streamlined instruction processor is proposed to process data in response to a program composed of prespecified instructions in pipeline cycles, which includes an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions from the instruction memory.
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