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Method and system for chalcogenide-based nanowire memory

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TLDR
In this paper, a method of manufacturing a memory circuit is implemented, which includes depositing nanoparticles at locations on a substrate using a vapor-liquid-solid technique, and lines are created to connect at least some of the chalcogenide-based nanowires.
Abstract
Chalcogenide-based nanowire memories are implemented using a variety of methods and devices. According to an example embodiment of the present invention, a method of manufacturing a memory circuit is implemented. The method includes depositing nanoparticles at locations on a substrate. Chalcogenide-based nanowires are created at the locations on the substrate using a vapor-liquid-solid technique. Insulating material is deposited between the chalcogenide-based nanowires. Lines are created to connect at least some of the chalcogenide-based nanowires.

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References
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Patent

Methods of fabricating nanostructures and nanowires and devices fabricated therefrom

TL;DR: One-dimensional nanostructures have uniform diameters of less than approximately 200 nm and are referred to as "nanowires" as mentioned in this paper, which include single-crystalline materials having different chemical compositions.
Patent

Preparation of carbide nanorods

TL;DR: In this article, a process utilizing a supported metal catalyst, a volatile species source, and a carbon source has been developed to produce carbide nanorods with diameters of less than about 100 nm and aspect ratios of 10 to 1000.
Patent

Method of producing metal oxide nanorods

TL;DR: The metal oxide nanorods have diameters between 1.5 and 200 nm and aspect ratios between 5 and 2000 as mentioned in this paper and can be used to produce large quantities of metal oxide nanoparticles.
Journal ArticleDOI

Synthesis and characterization of phase-change nanowires.

TL;DR: The synthesis and characterization of GeTe and Sb(2)Te(3) phase-change nanowires via a vapor-liquid-solid growth mechanism are reported, which have three different types of morphologies: single-crystalline straight and helical rhombohedral GeTe Nanowires and amorphous curly GeO(2).
Patent

Horizontal chalcogenide element defined by a pad for use in solid-state memories

TL;DR: In this paper, a process for fabricating phase-change elements having ultra small cross-sectional areas for use in phase change memory cells specifically and in semiconductor devices generally in which pads are implemented to create horizontally aligned phase change elements is disclosed.