Y
Y. Zhang
Researcher at IBM
Publications - 114
Citations - 3118
Y. Zhang is an academic researcher from IBM. The author has contributed to research in topics: Perovskite (structure) & Chemistry. The author has an hindex of 27, co-authored 44 publications receiving 2925 citations. Previous affiliations of Y. Zhang include Stanford University.
Papers
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Journal ArticleDOI
Polymer self assembly in semiconductor microelectronics
Charles T. Black,Ricardo Ruiz,Gregory Breyta,Joy Cheng,Matthew E. Colburn,Kathryn W. Guarini,Hyungjun Kim,Y. Zhang +7 more
TL;DR: Target applications including surface-roughening for on-chip decoupling capacitors, patterning nanocrystal floating gates for FLASH devices, and defining FET channel arrays are discussed.
Proceedings ArticleDOI
High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling
Sarunya Bangsaruntip,Guy M. Cohen,Amlan Majumdar,Y. Zhang,Sebastian Engelmann,Nicholas C. M. Fuller,Lynne Gignac,S. Mittal,J. Newbury,Michael A. Guillorn,Tymon Barwicz,Lidija Sekaric,Martin M. Frank,Jeffrey W. Sleight +13 more
TL;DR: In this article, undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling were demonstrated.
Proceedings ArticleDOI
Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs
Kern Rim,K.K. Chan,Leathen Shi,Diane C. Boyd,John A. Ott,N. Klymko,F. Cardone,Leo Tai,Steven J. Koester,Michael A. Cobb,Donald F. Canaperi,B. To,E. Duch,I. Babich,R. Carruthers,P. Saunders,G. Walker,Y. Zhang,Michelle L. Steen,Meikei Ieong +19 more
TL;DR: In this article, a tensile-strained Si layer was transferred to form an ultra-thin (<20 nm) strained Si directly on insulator (SSDOI) structure and electron and hole mobility enhancements were demonstrated.
Proceedings ArticleDOI
Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation
J. Kedzierski,Edward J. Nowak,T. Kanarsky,Y. Zhang,Diane C. Boyd,Roy A. Carruthers,C. Cabral,R. Amos,Christian Lavoie,Ronnen Andrew Roy,J. Newbury,E. Sullivan,J. Benedict,P. Saunders,Keith Kwong Hon Wong,Donald F. Canaperi,Mahadevaiyer Krishnan,K.-L. Lee,Beth Ann Rainey,David M. Fried,Peter E. Cottrell,Hon-Sum P. Wong,Meikei Ieong,Wilfried Haensch +23 more
TL;DR: In this paper, metal-gate FinFET and FDSOI devices were fabricated using total gate silicidation, and they satisfy the following metal gate technology requirements: ideal mobility, low gate leakage, high transconductance, competitive I/sub on/I/sub off, and adjustable V/sub t/.
Journal ArticleDOI
Process integration of self-assembled polymer templates into silicon nanofabrication
TL;DR: In this article, the processes used to achieve highly uniform nanoporous dielectric films, high-aspect-ratio nanotextured silicon, silicon nitride dot arrays, silicon pillar arrays, and silicon tip arrays are described.