Patent
Method for circuits connection for wafer level burning and testing of individual dies on semiconductor wafer
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TLDR
In this paper, a test circuit on a wafer is tested by the use of test circuits on the integrated circuit devices which is connected by means of a grid, and the response of the integrated circuits at different operating speeds is determined by the adjustment of the oscillator speed so that a timing signal used for the testing may be varied.Abstract:
Integrated circuit devices on a wafer are tested by the use of test circuit on the integrated circuit devices which is connected by means of a grid. The grid is used to enable the test circuitry, and provides an ability to test the devices while still on the wafer. This facilitates burning in the wafer prior to singulating the parts, since it is not necessary to separately establish electrical connections at contact points on the individual integrated circuit devices. In one embodiment, an oscillator may be adjusted in speed so that further tests may be effected by changing a test speed through the test circuit. Response of the integrated circuits at different operating speeds is determined by the adjustment of the oscillator speed so that a timing signal used for the testing may be varied.read more
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References
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Patent
Discrete die burn-in for nonpackaged die
TL;DR: In this paper, a reusable burn-in/test fixture for discrete TAB die consists of two halves, the first half contains cavity in which die is inserted, and the second half is a test fixture that establishes electrical contact with the die and with a burnin oven.
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John W. Jamison,Robert E. Allen +1 more
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