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Patent

Method for manufacturing an integrated circuit

Zhao Wang, +2 more
TLDR
In this article, a method for manufacturing an integrated circuit on a wafer comprises a first device of the integrated circuit is formed on the wafer, and a second device of integrated circuits is formed in order to make a projection area of the second device overlap with a projection of the first device partially or completely.
Abstract: 
Techniques related to a method for manufacturing an integrated circuit is disclosed. According to one embodiment, a method for manufacturing an integrated circuit on a wafer comprises a first device of the integrated circuit is formed on the wafer and a second device of the integrated circuit is formed on the wafer to make a projection area of the second device overlap with a projection area of the first device partially or completely. In one embodiment, two or more devices are formed in different layers of the integrated circuit, or formed at different depths in a same layer of the integrated circuit, so the two or more devices may share an area on the same wafer in a certain manner. Thereby, the area of the chip is saved and the chip cost of the integrated circuit is significantly reduced.

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Patent

Reduced mask CMOS salicided process

Shye-Lin Wu
TL;DR: In this paper, an ion implantation is performed to dope phosphorus into the substrate to form N well and then the oxide layer and the silicon nitride layer are respectively removed, a thin gate oxide is regrown on the surface of the substrate.
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Method of setting back bias of MOS circuit, and MOS integrated circuit

Masaharu Kubo, +3 more
TL;DR: In this article, a MOS circuit comprising a plurality of MOSFETs constituting a digital circuit, an input signal is supplied to the digital circuit and a first back bias voltage is supplied, so that a pn junction between the semiconductor substrate or semiconductor well region and a source region is brought to a forward voltage.
Patent

Plugged poly silicon resistor load for static random access memory cells

Robin W. Cheung, +1 more
TL;DR: In this article, an improved process for fabricating a static RAM cell having a polysilicon load resistance is provided, where a planarized dielectric structure is formed over the junction regions, and via openings which expose portions of the source and drain regions are created.
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P-well CMOS process using neutron activated doped N-/N+ silicon substrates

Emily A. Groves, +1 more
TL;DR: In this article, a 1 micrometer p-well process is used to build natural (unadjusted) PMOS transistors in the bulk silicon, which operate in the subthreshold region where the threshold or turn on voltages have to match closely across a large device.