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Patent

Method of error correction in a multi-bit-per-cell flash memory

TLDR
In this article, a plurality of bits related to the representation of the codeword is decoded iteratively, i.e., part or all of the representation itself or part of the results of preliminary processing of the original representation.
Abstract
Data are encoded as a systematic or nonsystematic codeword that is stored in a memory such as a flash memory. A representation of the codeword is read from the memory. A plurality of bits related to the representation of the codeword is decoded iteratively. The plurality of bits could be, for example, part or all of the representation of the codeword itself or part or all of the results of preliminary processing of part or all of the representation of the codeword.

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Citations
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Patent

Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated BCH codes and/or designation of “first below” cells

TL;DR: In this article, a method for decoding a plurality of flash memory cells which are error-correction-coded as a unit was proposed, the method comprising providing a hard decoding success indication indicating whether or not hard-decoding is at least likely to be successful.
Patent

Soft bit data transmission for error correction control in non-volatile memory

TL;DR: In this article, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements in order to adjust the reliability metrics for bits in code words which represent the sensed state.
Patent

Systems and methods for temporarily retiring memory portions

TL;DR: In this paper, the authors define at least one of the plurality of memory portions other than the certain portions as a retired memory portion for at least a first duration of time, and they define a controller operative to reserve for data retention purposes.
Patent

Systems and methods for averaging error rates in non-volatile devices and storage systems

TL;DR: In this article, a system for storing a plurality of logical pages in a set of at least one flash device, each flash device including an erase block in the set of erase blocks, is described.
Patent

Managing non-volatile media

TL;DR: In this paper, a method for determining a configuration parameter for a set of storage cells of a non-volatile recording medium is described, and a method to adjust the parameter based on read data is presented.
References
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Book

Low-Density Parity-Check Codes

TL;DR: A simple but nonoptimum decoding scheme operating directly from the channel a posteriori probabilities is described and the probability of error using this decoder on a binary symmetric channel is shown to decrease at least exponentially with a root of the block length.
Journal ArticleDOI

Near optimum error correcting coding and decoding: turbo-codes

TL;DR: A new family of convolutional codes, nicknamed turbo-codes, built from a particular concatenation of two recursive systematic codes, linked together by nonuniform interleaving appears to be close to the theoretical limit predicted by Shannon.
Book

Error Control Coding

Daniel Costello, +1 more
TL;DR: Error Control Coding (2nd Edition) by Shu Lin, Shu, Costello, Daniel J. Costello Jr. and a great selection of similar New, Used and Collectible.
Patent

Flash file system

TL;DR: The provision of a flash memory (12), virtual mapping system, which includes a flash controller (14) and a random access memory (16) for storing mapping tables, that allows data to be continuously written to unwritten physical address locations, is discussed in this paper.
Patent

Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states

TL;DR: In this article, the authors present a NAND type of flash EEPROM, where the memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed.