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Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (fpgas, dpgas, etc.)

Martin Vorbach, +1 more
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TLDR
In this article, a method of caching commands in microprocessors having a plurality of arithmetic units and in modules having a two- or multidimensional cell arrangement is provided, which includes combining the plurality of cells and arithmetic units to form groups, assigning a cache unit to a group, and connecting the cache unit with a higher level unit via a tree structure.
Abstract: 
A method of caching commands in microprocessors having a plurality of arithmetic units and in modules having a two- or multidimensional cell arrangement is provided. The method includes combining a plurality of cells and arithmetic units to form a plurality of groups, assigning a cache unit to a group, and connecting the cache unit to a higher level unit via a tree structure. The cache unit may send requests for required commands to the higher level cache unit, which may return a command sequence including the required command, if the higher level cache unit holds the first command sequence including the required command in the higher level cache unit's local memory.

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Patent

Optimization methods for the insertion, protection, and detection of digital watermarks in digitized data

Scott A. Moskowitz
TL;DR: In this article, the authors present methods and systems for encoding digital watermarks into content signals, including window identifier for identifying a sample window in the signal; an interval calculator for determining a quantization interval of the sample window; and a sampler for normalizing sample window to provide normalized samples.
Patent

Methods, systems and devices for packet watermarking and efficient provisioning of bandwidth

Scott A. Moskowitz
TL;DR: In this paper, the authors present methods and systems for transmitting streams of data, and also relate to generating packet watermarks and packet watermark keys, and an electronic method and system for purchasing good and services by establishing an account whereby a customer is credited with a predetermined amount of bandwidth usage.
Patent

Systems, methods and devices for trusted transactions

Scott A. Moskowitz
TL;DR: In this paper, the authors proposed a system for enhancing trust in transactions, most particularly in remote transactions between a plurality of transactional parties, for instance a seller and buyer(s) of goods and/or services over a public computer network such as the internet.
Patent

Multiple transform utilization and application for secure digital watermarking

Scott A. Moskowitz
TL;DR: In this paper, a fast Fourier transform is used to transform digital blocks in digital information to the frequency domain using a convolution mask from a key, and the chosen message information is encoded into each of the transformed digital blocks by altering the selected amplitudes based on the selected message information.
Patent

Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)

Martin Vorbach, +1 more
TL;DR: In this paper, the first result data may be obtained using a plurality of configurable coarse-granular elements, and the first results may be subsequently processed using the plurality of configured granular elements.
References
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Journal ArticleDOI

The program dependence graph and its use in optimization

Jeanne Ferrante, +2 more
- 01 Jul 1987 - 
TL;DR: An intermediate program representation, called the program dependence graph (PDG), that makes explicit both the data and control dependences for each operation in a program, allowing transformations to be triggered by one another and applied only to affected dependences.
Proceedings ArticleDOI

Garp: a MIPS processor with a reconfigurable coprocessor

Jay Hauser, +1 more
TL;DR: Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.
Patent

Configurable electrical circuit having configurable logic elements and configurable interconnects

Ross H. Freeman
TL;DR: In this article, a configurable logic array is defined as a plurality of logic elements that can be configured to perform different logic functions depending upon the control information placed in each logic element.
Patent

Network and intelligent cell for providing sensing bidirectional communications and control

Armas C. Markkula, +4 more
TL;DR: In this article, a plurality of intelligent cells, each comprising an integrated circuit having a processor and input/output sections are coupled in a network, each of the programmable cells includes a unique identification number (ID) at the time it is manufactured.
Proceedings Article

MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources

Ethan Mirsky, +1 more
TL;DR: MATRIX as discussed by the authors is a coarse-grained, reconfigurable com- puting architecture which supports confgurable instruction distribution, where device resources are allocated to control- ling and describing the computation on a per task basis.