Journal ArticleDOI
MIPSfpga: using a commercial MIPS soft-core in computer architecture education
Sarah L. Harris,David Harris,Daniel Chaver,Robert Owen,Zubair L. Kakakhel,Enrique Sedano,Yuri Panchul,Bruce Ableidinger +7 more
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TLDR
MIPSfpga is a teaching infrastructure that offers access to the non-obfuscated Register-Transfer Level (RTL) source code of the MIPS microAptiv UP processor, and its accompanying set of learning materials focus on hands-on learning that emphasises computer architecture, system on chip (SoC) design and hardware–software codesign.Abstract:
In this study, the authors introduce MIPSfpga and its accompanying set of learning materials. MIPSfpga is a teaching infrastructure that offers access to the non-obfuscated Register-Transfer Level (RTL) source code of the MIPS microAptiv UP processor. The core is made available by Imagination Technologies for academic use and is targeted to a field-programmable gate array (FPGA), making it ideal for both the classroom and research. The supporting materials and labs focus on hands-on learning that emphasises computer architecture, system on chip (SoC) design and hardware–software codesign. Among other things, students learn to set up the MIPS soft-core processor on an FPGA, run and debug programs on the core in simulation and in hardware, add new peripherals to the system, understand the microarchitecture and extend it to support new features, experiment with different cache sizes and content management policies, add new instructions using the CorExtend interface available in MIPS processors, and understand SoCs in embedded systems and how they are designed and built up in layers to run complex software such as Linux.read more
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Journal ArticleDOI
Systematic Approach for State-of-the-Art Architectures and System-on-Chip Selection for Heterogeneous IoT Applications
Ramesh Krishnamoorthy,Kalimuthu Krishnan,Bharatiraja Chokkalingam,Sanjeevikumar Padmanaban,Zbigniew Leonowicz,Jens Bo Holm-Nielsen,Massimo Mitolo +6 more
TL;DR: In this paper, a GA-based optimization method is used to select a specific system-on-chip (SoC) architecture for heterogeneous IoT applications, which is implemented in MATLAB to identify the optimized SoC architecture concerning device parameters such as a clock, cache, RAM space, external storage, network support, etc.
Proceedings ArticleDOI
RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education
Sarah L. Harris,Daniel Chaver,Luis Piñuel,Jose I. Gomez-Perez,M. Hamza Liaqat,Zubair L. Kakakhel,Olof Kindgren,Robert Owen +7 more
TL;DR: RISC-V FPGA Course as mentioned in this paper is a set of courses developed by the authors and Imagination Technologies that enable users to understand and use the RISC-v instruction set architecture (ISA), a commercial RISCV core and system, and the Risc-V ecosystem.
Journal ArticleDOI
Development of multiprocessor system-on-chip based on soft processor cores schoolMIPS
TL;DR: The obtained results suggest that there is a possibility of NoC development with the number of nodes up to 200 nodes on Stratix IV GX EP4SGX230 (DE4) and up to 1.54 Gbit/s with 10 processor cores.
Proceedings ArticleDOI
Practical experiences based on MIPSfpga
Daniel Chaver,Yuri Panchul,Enrique Sedano,David Harris,Robert Owen,Zubair L. Kakakhel,Bruce Ableidinger,Sarah L. Harris +7 more
TL;DR: MIPSfpga enabled students to bridge the gaps between theoretical concepts, hands-on practice, and industrial cores by allowing them to explore, modify, and test the MIPS core and system with the support of commercial compilers and tools
Journal ArticleDOI
Evolution of an educational microprocessor
TL;DR: The latest FPGA and SoC‐based implementations have shown further potential for students to acquire new knowledge in the field of microprocessor design, implementation, and verification.
References
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ReportDOI
The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0
TL;DR: RISC-V (pronounced risk-five) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education, but which it is hoped will become a standard open architecture for industry implementations.
Journal ArticleDOI
A Survey and Evaluation of Simulators Suitable for Teaching Courses in Computer Architecture and Organization
TL;DR: This paper attempts to give a survey of simulators suitable for teaching courses in computer architecture and organization, to establish the evaluation criteria and to evaluate selected simulators according to these criteria.
Journal ArticleDOI
An FPGA‐based integrated environment for computer architecture
TL;DR: A new, integrated environment used in computer‐architecture education is presented that makes it possible to download the students' programs to the FPGA‐based microprocessor and graphically depicts the processor's internal state on the PC.
Journal ArticleDOI
An integrated laboratory for processor organization, compiler design, and computer networking
TL;DR: An integrated laboratory dealing with processor organization, compiler design, and computer networking has been developed to make it possible for each student to work with modern and attractive materials and to learn about the interfaces between system modules.
Proceedings ArticleDOI
BZK.SAU: Implementing a hardware and software-based Computer Architecture simulator for educational purpose
TL;DR: This paper presents a computer architecture simulator design named BZK.SAU, which has fifty-nine instructions that are commonly used in commercial microprocessors and has eleven registers and implements interrupt, stack and input-output operations.