Open AccessProceedings Article
Model for Delay Faults Based Upon Paths
Gordon L. Smith
- pp 342-351
TLDR
A procedure is described which identifies paths which are tested for path faults by a set of patterns, independent of the delays of any individual gate of the network, which is a global delay fault model.Abstract:
Delay testing of combinational logic in a clocked environment is analyzed. A model based upon paths is introduced for delay faults. Any path with a total delay exceeding the clock interval is called a "path fault." This is a global delay fault model because it is associated with an entire path. The more familiar slow-to-rise or slow-to-fall gate delay fault, on the other hand, is a local fault model. A procedure is described which identifies paths which are tested for path faults by a set of patterns. It does not involve delay simulation. The paths so identified are tested for path faults independent of the delays of any individual gate of the network.read more
Citations
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On Delay Fault Testing in Logic Circuits
Chin Jen Lin,Sudhakar M. Reddy +1 more
TL;DR: Algorithms, based on a five-valued logic system, to accurately calculate the detection probability of path delay faults by random delay tests as well as to derive deterministic tests to detect pathdelay faults are proposed.
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Transition Fault Simulation
TL;DR: The authors present a model, called a transition fault, which when used with parallel-pattern, single-fault propagation, is an efficient way to simulate delay faults and shows that delay fault simulation can be done of random patterns in less than 10% more time than needed for a stuck fault simulation.
Journal ArticleDOI
Broad-side delay test
Jacob Savir,S. Patil +1 more
TL;DR: It is shown that the broad-side method is inferior to the skewed-load method, which is another form of scan-based transition test, and there is, however, a merit in combining the skewed -load method with the broad -side method to achieve a higher transition fault coverage.
Journal ArticleDOI
Scan-based transition test
Jacob Savir,S. Patil +1 more
TL;DR: In this paper, several issues of skewed-load transition test are investigated, such as transition test calculus, detection probability of transition faults, transition fault coverage, and enhancement of transition test quality.
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Proceedings ArticleDOI
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T. M. Storey,J. W. Barry +1 more
TL;DR: The delay test simulator described here has two functions: first, it computes the actual timing to be used for each delay test, and second, it performs a parallel fault simulation to determine which delay faults have been detected.