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Open AccessJournal ArticleDOI

Modeling Method to Develop an AMBA AXI4 Bus Interconnect: A Survey

Harini H G, +1 more
- 28 Apr 2015 - 
- Vol. 4, Iss: 04
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TLDR
This analysis comes to the conclusion that using TLM method increases the simulation speed, and reduces the effort due to the availability of open source packages which can support the Transaction Level modeling (TLM) method.
Abstract
Due to the increased customer demands design complexity of system on chip (SOC) increases day by day. Hence there is always a productivity gap [8].To address this issue various advanced methods are adopted during the design, development and verification phase of any project. It might be developing an Intellectual property (IP), using an automated tool, hardware software co design or using various modeling methodologies [8] at the earlier phase of the project for system level architecture exploration. In this paper we are discussing two modeling techniques to develop and verify the Advanced Extensible interface (AXI4) bus interconnect , they are Register Transfer level (RTL) method and Transaction Level modeling (TLM) method. From this analysis we come to the conclusion that using TLM method increases the simulation speed, and reduces the effort due to the availability of open source packages which can support the Transaction Level modeling (TLM) method Keywords—Register Transfer level (RTL), Transaction Level modeling (TLM), Intellectual property (IP), Advanced Extensible interface (AXI), System On Chip (SOC), Advanced Micro Controller Bus Architecture (AMBA), CORE CONNECT, Result oriented model (ROM), Instruction Set Simulator (ISS), International Business Machine (IBM),s Cycle Aaccurate (CA).

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Book ChapterDOI

An FPGA Implementation of Rapid Switch Module for EtherCAT Slave Controller

TL;DR: This paper uses FPGA to achieve high-performance cycle times for EtherCAT Slave Controller (ESC) internal data switch between ports, and introduces the implementation of the EtherCat slave controller’s rapid switch module.
References
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Proceedings ArticleDOI

Transaction-based SoC design techniques for AMBA AXI4 bus interconnects using VHDL

TL;DR: This paper introduces a technique to develop transaction-based hardware that brings the benefits of transaction- based verification (TBV) to the hardware design engineers, resulting in a greater level of simplification for complex designs.