Journal ArticleDOI
Network subsystem design
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It is argued that the bandwidth of the CPU/memory data path on workstations will remain within the same order of magnitude as the network bandwidth delivered to the workstation, and it is essential that the number of times network data traverses theCPU/ memory data path be minimized.Abstract:
It is argued that the bandwidth of the CPU/memory data path on workstations will remain within the same order of magnitude as the network bandwidth delivered to the workstation. This makes it essential that the number of times network data traverses the CPU/memory data path be minimized. Evidence which suggests that the cache cannot be expected to significantly reduce the number of data movements over this path is reviewed. Hardware and software techniques for avoiding the CPU/memory bottleneck are discussed. It is concluded that naively applying these techniques is not sufficient for achieving good application-to-application throughput; they must also be carefully integrated. Various techniques that can be integrated to provide a high bandwidth data path between I/O devices and application programs are outlined. >read more
Citations
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Journal ArticleDOI
The design of the TAO real-time object request broker
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Proceedings ArticleDOI
Fbufs: a high-bandwidth cross-domain transfer facility
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Patent
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Patent
Multiple network protocol encoder/decoder and data processor
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References
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TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Proceedings ArticleDOI
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Journal ArticleDOI
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