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Proceedings ArticleDOI

New placement and global routing algorithms for standard cell layouts

Masato Edahiro, +1 more
- pp 642-645
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TLDR
New placement and global routing algorithms are proposed for standard cell layouts that are effective to avoid being trapped in local optimum solutions and are simple and highly efficient.
Abstract
New placement and global routing algorithms are proposed for standard cell layouts. The placement algorithm, called the hierarchical clustering with min-cut exchange (HCME), is effective to avoid being trapped in local optimum solutions. The global routing algorithm does not route the nets one by one and therefore, the results are independent of the net order and channel order. In this algorithm, channel width is minimized under a cost function, in which the trade-off between the minimization of net lengths and the minimization of the number of tracks is considered. These algorithms are simple and highly efficient. This is confirmed by computational experiments.

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Citations
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Patent

Efficient scatternet forming

TL;DR: In this article, two logically separated scatternets, the maximum connectivity scattternet (MCS) and the traffic scatteret (TS), are provided. But the MCS is maintained autonomously as new nodes arrive to the scatchternet and other nodes leave the scatterternet.
Proceedings ArticleDOI

A cell-replicating approach to minicut-based circuit partitioning

TL;DR: An extension to the Fiduccia and Mattheyses minicut algorithm (1982) allows cells to be replicated in both sides of the partition and can substantially reduce the number of cut nets in a partitioned network below what can be obtained without replication.
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Edge separability-based circuit clustering with application to multilevel circuit partitioning

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Two-dimensional layout synthesis for large-scale CMOS circuits

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Fault behavior dictionary for simulation of device-level transients

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References
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Proceedings ArticleDOI

A new global router for row-based layout

TL;DR: A global router for row-based layout styles such as sea-of-gates, gate-array, and standard cell circuits is discussed, generalized to handle macro blocks on the chip, equivalent sets of pins, single pins (those without an equivalent), and circuits having many or no built-into-the-cell feeds.
Book ChapterDOI

GORDIAN: a new global optimization/rectangle dissection method for cell placement

TL;DR: A placement method for cell-based layout styles composed of alternating and interacting global optimization and partitioning phases is presented, which maintains the simultaneous treatment of all cells during optimization over all levels of partitioning.
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