Patent
Optimization of cell subtypes in a hierarchical design flow
Frederik Eaton,Peter A. Beerel +1 more
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TLDR
In this article, a plurality cell instances are organized hierarchically, each cell instance corresponds schematically to one of a plurality of cell types, and each cell subtype corresponding to a particular cell type differs from all other cell subtypes corresponding to the particular cell types by at least one transistor dimension.Abstract:
Methods and apparatus are described for facilitating physical synthesis of a circuit design. The circuit design includes a plurality cell instances organized hierarchically. Each cell instance corresponds schematically to one of a plurality of cell types. Transistors in each of the cell instances is sized with reference to an objective function thereby resulting in a first plurality of cell subtypes for each cell type. Each cell subtype corresponding to a particular cell type differs from all other cell subtypes corresponding to the particular cell type by at least one transistor dimension. Selected ones of the subtypes for at least one of the cell types are merged thereby resulting in a second plurality of subtypes for the at least one of the cell types. The second plurality of subtypes being fewer than the first plurality of subtypes. The merging of the selected subtypes achieves a balance between the objective function and a cost associated with maintaining the selected subtypes distinct.read more
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Patent
Dynamic array architecture
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References
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Compiling Communicating Processes into Delay-Insensitive VLSI Circuits
TL;DR: The circuits obtained are delay-insensitive, i.e., their correct operation is independent of any assumption on delays in operators and wires, except that the delays are finite.
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TL;DR: A design style for implementing communicating sequential processes (CSP) as quasi delay insensitive asynchronous circuits, based on the compilation method of [1], which can easily implement circuits with some slack between inputs and outputs is presented.
Patent
Method and apparatus for fair and efficient scheduling of variable-size data packets in an input-buffered multipoint switch
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Q-modules: internally clocked delay-insensitive modules
TL;DR: Prototypes of components to implement Q-modules have been designed, and a design aid program, QSYN, to place instances of these components, personalize a PLA, and generate a MAGIC or CIF file for a CMOS realization is being developed.