Proceedings ArticleDOI
Oscillation-based Test for Measuring 1dB Gain Compression Point of Power Amplifiers
Saeedeh Makhsuci,Mehdi Ehsanian +1 more
- pp 190-195
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TLDR
In this article, a new method to measure the 1dB gain compression point (PldB) for a 5.8GHz power amplifier was proposed based on oscillation built-in self-test (OBIST) method.Abstract:
This paper describes a new method to measure the 1dB gain compression point (PldB) for a 5.8GHz power amplifier (PA). The proposed method is based on oscillation built-in self-test (OBIST) method. The circuit is designed in 180nm CMOS technology. The PA is transformed into an oscillator and growing PA input amplitude is produced without an external signal generator. This technique offers a proper growth rate of the PA input voltage amplitude with a proper operating frequency. Using this method, PldB occurs when the voltage input amplitude is 460.5mV. Finally, the new quasi OBIST method can measure the voltage input amplitude where the PldB occur with approximately 2% error.read more
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References
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A BIST scheme for an SNR test of a sigma-delta ADC
M.F. Toner,Gordon W. Roberts +1 more
TL;DR: The MAD-BIST strategy for the SNR test of the A/D converter is introduced, accuracy issues are discussed, and experimental results are presented.
Proceedings ArticleDOI
Oscillation built-in self test (OBIST) scheme for functional and structural testing of analog and mixed-signal integrated circuits
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TL;DR: A new built-in self test (BIST) technique suitable for both functional and structural testing of analog and mixed-signal circuits based on the oscillation-test methodology is described.
Proceedings ArticleDOI
A built-in self-test circuit for measuring 1dB gain compression point of power amplifiers
Saeedeh Makhsuci,Mehdi Ehsanian +1 more
TL;DR: A built-in self-test (BIST) circuit is designed in 180nm CMOS technology to measure the compression point of a power amplifier (PA) working in 5.8GHz.
Proceedings ArticleDOI
Testing of low voltage two stage operational amplifier using oscillation test methodology
Maninder Kaur,Jasdeep Kaur +1 more
TL;DR: Discrete practical realizations and extensive simulations based on CMOS 1μm technology parameters using PSPICE affirm that the test technique presented for MOSFET circuits ensures high fault coverage and requires a negligible area overhead.
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TL;DR: This study shows that the maximum for the conversion gain occurs in the moderate inversion region and the output Signal to Noise Ratio is shown to be maximum in themoderate to weak inversion regions.