Patent
Packaging an integrated circuit die with backside metallization
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TLDR
In this article, a method of packaging integrated circuit (IC) dies is described, which includes applying a laminating material ( 44 ) to a wafer and separating the wafer into multiple IC dies such that the lamination material is applied to back surfaces ( 52 ) of the IC dies.Abstract:
A method ( 32 ) of packaging integrated circuit (IC) dies ( 48 ) includes applying ( 36 ) a laminating material ( 44 ) to a wafer ( 40 ), and separating ( 46 ) the wafer ( 40 ) into multiple IC dies ( 48 ) such that the laminating material ( 44 ) is applied to back surfaces ( 52 ) of the IC dies ( 48 ). Each of the IC dies ( 48 ) is positioned ( 62 ) with an active surface ( 50 ) facing a support substrate ( 56 ). An encapsulant layer ( 72 ) is formed ( 64 ) overlying the laminating material ( 44 ) and the back surfaces ( 52 ) of the IC dies ( 48 ) from a molding compound ( 66 ). The molding compound ( 66 ) and the laminating material ( 44 ) are removed from the back surfaces ( 52 ) of the IC dies ( 48 ) to form ( 76 ) openings ( 78 ) exposing the back surfaces ( 52 ). Conductive material ( 84, 88 ) is placed in the openings ( 78 ) and functions as a heat sink and/or a ground for the IC dies ( 48 ).read more
Citations
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References
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Patent
Circuit device with at least partial packaging and method for forming
George R. Leal,Jie-Hua Zhao,Edward R. Prack,Robert J. Wenzel,Brian D. Sawyer,David G. Wontor,Marc A. Mangrum +6 more
TL;DR: In this paper, a circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device is coplanar with the conductive surface (10).
Patent
Circuit device with at least partial packaging, exposed active surface and a voltage reference plane
George R. Leal,Jie-Hua Zhao,Edward R. Prack,Robert J. Wenzel,Brian D. Sawyer,David G. Wontor,Marc A. Mangrum +6 more
TL;DR: In this paper, a circuit device (15 ) is placed within an opening of a conductive layer (10 ) which is then partially encapsulated with an encapsulant ( 24 ) so that the active surface of the circuit device is coplanar with the conductive surface (10 ).
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Embedded actives and discrete passives in a cavity within build-up layers
TL;DR: In this article, the authors describe an electronic system or module which includes embedded actives and discrete passives, and methods for use in fabricating packages containing embedded active devices and/or discrete passive devices.
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Raymond Albert Fillion,Richard Alfred Beaupre,Ahmed Elasser,Robert John Wojnarowski,Charles Steven Korman +4 more
TL;DR: A semiconductor chip packaging structure comprising a dielectric film 10 having one or more through holes 11 aligned with the contact pads 22 and 23 of at least one power SINR chip 21 is described in this article.
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Power semiconductor module and fabrication method
Eladio Clemente Delgado,Richard Alfred Beaupre,Stephen Daley Arthur,Ernest Wayne Balch,Kevin Matthew Durocher,Paul Alan Mcconnelee,Raymond Albert Fillion +6 more
TL;DR: A power semiconductor module as mentioned in this paper consists of an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion with a thickness thinner than that of the power coupling component.