Patent
Paired instruction processor precise exception handling mechanism
TLDR
In this paper, a mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for single instructions is presented.Abstract:
A mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for single instructions. The mechanism detects an exception associated with one of the instructions in the family, inhibits the data writes for the instructions in the family, flushes the pipeline, and reissues the instruction singly. The exception handling procedure for the single instruction may then be utilized.read more
Citations
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Patent
Resynchronisation of a superscalar processor
Scott A. White,Michael D Goddard +1 more
TL;DR: In this article, a pipeline processor (110) is resynchronized under designated conditions by updating a fetch program counter (210) and fetches instructions from a memory (114).
Patent
Processor structure and method for maintaining and restoring precise state at any instruction boundary
TL;DR: In this paper, a high-performance processor is disclosed with structure and methods for: (1) aggressively scheduling long latency instructions including load/store instructions while maintaining precise state; (2) maintaining and restoring precise state at any instruction boundary; (3) tracking instruction status to maintain precise state.
Patent
Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
Abstract: The parallelism of a multi-pipelined digital computer is enhanced by detection of branch instructions from the execution pipelines and concurrent processing of up to two of the detected instructions in parallel with the operations of the execution pipelines. Certain branch instructions, when detected, are removed altogether from the pipeline, but still processed. The processing is synchronized with the execution pipeline to, first, predict an outcome for detected branch instructions, second, test the conditions for branch instructions at their proper place in the execution sequence to determine whether the predicted outcome was correct, and third, fetch a corrected target instruction if the prediction proves wrong.
Patent
Central processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution
TL;DR: In this paper, an apparatus and method for scheduling a sequence of instructions for achieving multiple launches and multiple executions of the instructions within a central processing unit within a single processor is presented.
Patent
Recovery method and apparatus for a pipelined processing unit of a multiprocessor system
Barlow George J,James W. Keeley,Richard A. Lemay,Jian-Kuo Shen,Robert V. Ledoux,Thomas F. Joyce,Richard P. Kelly,Robert C. Miller +7 more
TL;DR: In this paper, the UEV detector circuits are used to detect UEV faults in the pipelined central processing system (CSS) units of a multiprocessor system, which are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices.
References
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Patent
System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer
David A. Webb,David B. Fite,Ricky C. Hetherington,Francis X. McKeen,Mark A. Firstenberg,John E. Murray,Dwight P. Manley,Ronald M. Salett,Tryggve Fossum +8 more
TL;DR: In this article, a technique for processing memory access exceptions along with pre-fetched instructions in a pipelined instruction processing computer system is based upon the concept of pipelining exception information along with other parts of the instruction being executed.
Patent
Method and apparatus for validating prefetched instruction
TL;DR: In this article, a method and data processing system for validating prefetch instruction is presented, which includes an instruction unit, an n-stage pipeline which provides data segments representing instruction words from a memory to the instruction unit and a circuit for verifying the validity of the prefetched instruction word prior to execution by the execution unit.
Patent
Vector processor capable of parallely executing instructions and reserving execution status order for restarting interrupted executions
TL;DR: In this paper, a vector processor is defined as a processor in which a plurality of data are processed by one instruction and a majority of instructions are parallely processed, and the stored information is used to restart the execution of the interrupted program at the appropriate point.
Patent
Method and device to execute two instruction sequences in an order determined in advance
TL;DR: In this paper, a data processing system executes two instruction sequences in an order determined in advance, with the aid of the instructions, a separate memory assigned to respective sequence is activated for data information reading/writing.
Patent
Apparatus for invalidating the content of an instruction buffer by program store compare check
TL;DR: In this paper, inconsistency between an instruction stored in a main memory and the same instruction present in the instruction buffer occurs at the time of a store operation to the memory if the instruction supplied to the store area of the main memory previously has been prefetched to and is present in an instruction buffer.
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