Proceedings ArticleDOI
Parallel Memory Implementation for Arbitrary Stride Accesses
Eero Aho,Jarno Vanne,Timo Hämäläinen +2 more
- pp 1-6
TLDR
The proposed novel parallel memory implementation allows conflict free accesses with all the constant strides which has not been possible in prior application specific parallel memories.Abstract:
Parallel memory modules can be used to increase memory bandwidth and feed a processor with only necessary data Arbitrary stride access capability with interleaved memories is described in previous research where the skewing scheme is changed at run time according to the currently used stride This paper presents the improved schemes which are adapted to parallel memories The proposed novel parallel memory implementation allows conflict free accesses with all the constant strides which has not been possible in prior application specific parallel memories Moreover, the possible access locations are unrestricted and the data patterns have equal amount of accessed data elements as the number of memory modules Timing and area estimates are given for Altera Stratix FPGA and 018 micrometer CMOS process with memory module count from 2 to 32 The FPGA results show 129 MHz clock frequency for a system with 16 memory modules when read and write latencies are 3 and 2 clock cycles, respectivelyread more
Citations
More filters
Design and Implementation of Parallel Memory Architectures
TL;DR: A chronology of key events and figures leading up to and including the invention of the atomic bomb and its use in World War Two are listed.
Journal ArticleDOI
Parallel Memory Architecture for Application-Specific Instruction-Set Processors
TL;DR: A conflict resolving parallel data memory system for application-specific instruction-set processors is described and it is shown that significant power savings can be obtained by exploiting the parallel memory system instead of multi-port memory.
Journal ArticleDOI
Configurable data memory for multimedia processing
TL;DR: The proposed novel parallel memory implementation allows conflict free accesses with all the constant strides which has not been possible in prior application specific parallel memories.
Patent
Memory with programmable strides
TL;DR: In this article, the authors present a storage configured to store and output multiple address strides of varying sizes to enable access and precharge circuitry to access and charge a first and a second group of memory cells based at least in part on the multiple addresses during operation of the host apparatus/system.
Journal ArticleDOI
Partial access conflict-relieving programmable address shuffler for parallel memory system in multi-core processor
Young-Su Kwon,Nak-Woong Eum +1 more
TL;DR: This work proposes and evaluates the programmable memory address shuffler associated with the novel memory shuffling algorithm integrated in multi-core architecture with parallel memory system, and demonstrates that the shuffled sub-pages are represented by cyclic linked list which enables partial address shuffling with the minimal number of shuffling table entries reducing hardware complexity.
References
More filters
Journal ArticleDOI
The Organization and Use of Parallel Memories
Paul Budnik,David J. Kuck +1 more
TL;DR: As computer CPUs get faster, primary memories tend to be organized in parallel banks, and important questions of design and use of such memories are discussed.
Journal ArticleDOI
Conflict-free vector access using a dynamic storage scheme
D.T. Harper,D.A. Linebarger +1 more
TL;DR: Simulation results show that if a single buffer is added to each memory port, then the average performance of the dynamic scheme surpasses that of the interleaved scheme for arbitrary stride accesses.
Patent
Dynamic address mapping for conflict-free vector access
TL;DR: In this article, a storage scheme for each vector based on the accessing patterns to be used with that vector is selected to provide conflict-free access for a predetermined stride S. The storage scheme involves a rotation or permutation of an addressed row of corresponding memory locations in N parallel modules in main memory.
Journal ArticleDOI
Multimedia rectangularly addressable memory
TL;DR: A scalable data alignment scheme incorporating module assignment functions and a generic addressing function for parallel access of randomly aligned rectangular blocks of data is proposed and speedups close to 8/spl times/ can be expected when compared to linear addressing schemes.