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Patent

Pattern correction method, apparatus, and program

TLDR
In this article, an environmental profile is determined based on whether or not another graphics pattern exists at the surroundings of each correction target cell included in the entered design layout data, and a target cell name is replaced with a prescribed cell name of correction pattern corresponding to the determined environmental profile by referencing a cell replacement table.
Abstract
In a pattern correction method, design layout data of a pattern designed by an automated layout unit is entered. An environmental profile is determined based on whether or not another graphics pattern exists at the surroundings of each correction target cell included in the entered design layout data. A target cell name is replaced with a prescribed cell name of correction pattern corresponding to the determined environmental profile by referencing a cell replacement table. An OPC correction pattern corresponding to the replaced cell name is imported from a cell library.

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Patent

Dynamic array architecture

TL;DR: In this paper, a linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrodes segments within the linear-gated electrode track, while ensuring adequate electrical isolation between the adjacent linear gated electrode segments.
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Method of IC fabrication, IC mask fabrication and program product therefor

TL;DR: In this article, a method of forming IC chip shapes and a method and computer program product for converting an IC design to a mask, e.g., for standard cell design, are presented.
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Methods for Defining Dynamic Array Section with Manufacturing Assurance Halo and Apparatus Implementing the Same

TL;DR: In this paper, a method for defining a dynamic array section to be manufactured on a semiconductor chip is described, which includes defining a peripheral boundary of the dynamic array and a manufacturing assurance halo outside the boundary.
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Methods for defining contact grid in dynamic array architecture

TL;DR: In this article, the vertical connection structures are placed at a number of gridpoints within a vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels.
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Cell circuit and layout with linear finfet structures

TL;DR: In this paper, a cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other.
References
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Patent

General purpose shape-based layout processing scheme for IC layout modifications

TL;DR: In this article, a shape can be defined by a set of associated edges in a specified configuration, and a catalog of shapes is defined and layout processing actions are associated with the various shapes.
Patent

Selection of evaluation point locations based on proximity effects model amplitudes for correcting proximity effects in a fabrication layout

TL;DR: In this article, a dissection length parameter is derived based on a profile of amplitudes output by a proximity effects model along a transect, and then it is determined how to correct at least a portion of the first edge for proximity effects based on an analysis at the evaluation point.
Patent

System and method for preparing shape data for proximity correction

TL;DR: In electron beam lithography, an apparatus and method decompose rectangles at the exterior of a desired electron beam exposure pattern into portions having a substantially constant environment, and then the resulting rectangles indicate the edge(s) of the rectangle at which cuts were made to form the rectangle as discussed by the authors.
Patent

Conducting automatic correction processing

TL;DR: In this paper, a correction target segment extracted from the design pattern is divided into lengths suited for correction, and a correction value is obtained by two-dimensionalally extracting a pattern included in a rectangular region having a predetermined distance from one point on the divided segment in perpendicular and horizontal directions.
Patent

Proximity correction system for wafer lithography

TL;DR: In this paper, a system for computing a pattern function for a polygonal pattern having a finite number of predetermined face angles is presented, which includes the steps of decomposing the polygon into a set of flashes, computing the pattern function by summing together all flashes evaluated at a point (x,y), and returning a 1 if a point is inside a polygons and otherwise will return a 0.