M
Mutsunori Igarashi
Researcher at Toshiba
Publications - 36
Citations - 2200
Mutsunori Igarashi is an academic researcher from Toshiba. The author has contributed to research in topics: Integrated circuit & Codec. The author has an hindex of 18, co-authored 36 publications receiving 2189 citations.
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Patent
Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
Mutsunori Igarashi,Takashi Mitsuhashi,Masami Murakata,Masaaki Yamada,Fumihiro Minami,Toshihiro Akiyama,Takahiro Aoki +6 more
TL;DR: In this paper, an X-Y reference wiring grid using wirings of a total of M (M ≥ 2) layers in which an n-th (n≧2) layer wiring intersects orthogonally with a (n−1)-th layer wiring, and forms an oblique wiring grid which intersects with the reference wiring layer to have an angle of 45 degree or 135 degree.
Journal ArticleDOI
Automated low-power technique exploiting multiple supply voltages applied to a media processor
Kimiyoshi Usami,Mutsunori Igarashi,Fumihiro Minami,Takashi Ishikawa,M. Kanzawa,Makoto Ichida,Kazutaka Nogami +6 more
TL;DR: An automated design technique to reduce power by making use of two supply voltages, which was applied to a media processor chip and reduced the power by 47% in random-logic modules and by 73% in the clock tree, while keeping the performance.
Patent
Arrangement method for logic cells in semiconductor IC device
Mutsunori Igarashi,Kaori Kora +1 more
TL;DR: In this paper, an arrangement method for logic cells in a semiconductor IC device, in which a plurality of logic cells are arranged on a chip and wiring is performed between the logic cells so as to realize a desired circuit, comprises the steps of developing the logic cell informations to be arranged on the chip and already-arranged cell and wiring informations into connection pins and inhibited areas for wiring.
Proceedings ArticleDOI
Automated low-power technique exploiting multiple supply voltages applied to a media processor
Kimiyoshi Usami,Kazutaka Nogami,Mutsunori Igarashi,Fumihiro Minami,Yukio Kawasaki,Takashi Ishikawa,Masahiro Kanazawa,Takao Aoki,Midori Takano,Chiharu Mizuno,Makoto Ichida,Shinji Sonoda,M. Takahashi,N. Hatanaka +13 more
TL;DR: An automated design technique to reduce power by making use of two supply voltages by combining structure synthesis, placement and routing and random logic modules of a media processor chip.
Patent
Pattern correction method, apparatus, and program
TL;DR: In this article, an environmental profile is determined based on whether or not another graphics pattern exists at the surroundings of each correction target cell included in the entered design layout data, and a target cell name is replaced with a prescribed cell name of correction pattern corresponding to the determined environmental profile by referencing a cell replacement table.