Journal ArticleDOI
Performance improvements to VLSI parallel systems, using dynamic concatenation of processing resources
Daniel Audet,Yvon Savaria,Jean-Louis Houle +2 more
- Vol. 18, Iss: 2, pp 149-167
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TLDR
It is shown that DCA significantly improves performance in systems where I/O bottlenecks exist, and a model for evaluating the performance speed-ups that could be achieved using DCA is developed.Abstract:
This paper presents a new approach for improving the efficiency of large VLSI parallel systems called the Dynamic Concatenation Approach (DCA). The basic idea of DCA is to concatenate bit-serial processing elements to construct bit-parallel processors of variable width. The concatenation permits an increase in the storage capacity of each processor which can be used to keep a number of local variables within the processor registers. A model for evaluating the performance speed-ups that could be achieved using DCA is developed. Arbitrary architectural characteristics as well as program characteristics are both taken into account in this model. Speed-up estimates are obtained by considering the effect of DCA when the variables of three programs are allocated to the registers of the processing elements. It is shown that DCA significantly improves performance in systems where I/O bottlenecks exist.read more
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Dissertation
Abacus: a reconfigurable bit-parallel architecture for early vision
TL;DR: This thesis develops Abacus, a high-speed reconngurable SIMD (single-instruction, multiple-data) architecture that outperforms conventional microprocessors by over an order of magnitude using the same silicon resources.
References
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Why systolic architectures
TL;DR: The basic principle of systolic architectures is reviewed and it is explained why they should result in cost-effective, highperformance special-purpose systems for a wide range of problems.
Book
The Connection Machine
TL;DR: The Connection Machine describes a fundamentally different kind of computer that Daniel Hillis and others are now developing to perform tasks that no conventional, sequential machine can solve in a reasonable time.
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The ILLIAC IV Computer
TL;DR: The structure of ILLIAC IV, a parallel-array computer containing 256 processing elements, is described, special features include multiarray processing, multiprecision arithmetic, and fast data-routing interconnections.
Journal ArticleDOI
The Warp Computer: Architecture, Implementation, and Performance
Marco Annaratone,E. Arnould,Thomas Gross,Hsiang-Tsung Kung,Monica S. Lam,O. Menzilcioglu,Jon A. Webb +6 more
TL;DR: The architecture, implementation, and performance of the Warp machine is described, demonstrating that the Warp architecture is effective in the application domain of robot navigation as well as in other fields such as signal processing, scientific computation, and computer vision research.