Proceedings ArticleDOI
POSTER: Fault-tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support
Florian Haas,Sebastian Weis,Theo Ungerer,Gilles Pokam,Youfeng Wu +4 more
- pp 421-422
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TLDR
This work proposes a software/hardware hybrid approach, which leverages Intel's hardware transactional memory (TSX) to support implicit checkpoint creation and fast rollback, leading to a resulting performance overhead of 19% on average.Abstract:
Software-based fault-tolerance mechanisms can increase the reliability of multi-core CPUs while being cheaper and more flexible than hardware solutions like lockstep architectures. However, checkpoint creation, error detection and correction entail high performance overhead if implemented in software. We propose a software/hardware hybrid approach, which leverages Intel's hardware transactional memory (TSX) to support implicit checkpoint creation and fast rollback. Hardware enhancements are proposed and evaluated, leading to a resulting performance overhead of 19% on average.read more
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Book ChapterDOI
Fault-Tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support
TL;DR: This paper proposes a software/hardware hybrid approach, which targets Intel’s current x86 multi-core platforms of the Core and Xeon family, and leverage hardware transactional memory (Intel TSX) to support implicit checkpoint creation and fast rollback.
References
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Proceedings ArticleDOI
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TL;DR: The concept of the sphere of replication is introduced, which abstract both the physical redundancy of a lockstepped system and the logical redundancy of an SRT processor, and two mechanisms-slack fetch and branch outcome queue-are proposed and evaluated that enhance the performance of anSRT processor by allowing one thread to prefetch cache misses and branch results for the other thread.
Book
Architecture Design for Soft Errors
TL;DR: This book provides a comprehensive description of the architetural techniques to tackle the soft error problem, and covers the new methodologies for quantitative analysis of soft errors as well as novel, cost-effective architectural techniques to mitigate them.