Patent
Process for forming front-back through contacts in micro-integrated electronic devices
Ubaldo Mastromatteo,Bruno Murari +1 more
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TLDR
In this paper, the authors describe the process of forming a through hole from the back of a semiconductor material body, forming a hole insulating layer of electrically isolating material laterally covering the walls of the hole, and forming a connection structure extending on top of the upper surface of the body between and in electrical contact with the through contact region and the electronic component.Abstract:
The process comprises the steps of: forming a through hole from the back of a semiconductor material body; forming a hole insulating layer of electrically isolating material laterally covering the walls of the through hole; forming a through contact region of conductive material laterally covering the hole insulating layer inside the hole and having at least one portion extending on top of the lower surface of the body; forming a protective layer covering the through contact region; and forming a connection structure extending on top of the upper surface of the body between and in electrical contact with the through contact region and the electronic component.read more
Citations
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Through-wafer interconnects for photoimager and memory wafers
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References
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Proceedings ArticleDOI
Fabrication technology for wafer through-hole interconnections and three-dimensional stacks of chips and wafers
TL;DR: In this paper, the authors present an approach to build electronic systems with very high chip count, where individual dies, blocks of dies and ultimately entire wafers are stacked on top of each other.
Patent
Integrated circuit and method
TL;DR: In this article, the authors present a fabrication method incorporating two-terminal devices such as IMPATT diodes (446) and Schottky Diodes(454) in a monolithic integrated circuit.
Patent
Method for forming deep conductive feedthroughs
TL;DR: In this article, an opening is etched through the silicon layer with KOH to provide an inwardly sloping sidewall profile having an angle that is approximately equal to 54.7 degrees.
Journal ArticleDOI
Method for producing via-connections in semiconductor wafers using a combination of plasma and chemical etching
TL;DR: A via-connection is formed in a silicon wafer by metallization of a plasma etched groove followed by chemical etching of the opposite surface of the wafer up to the top of the metallized groove and by patterning a contact pad as mentioned in this paper.