Book ChapterDOI
Reconstructing hardware transactional memory for workload optimized systems
Kunal Korgaonkar,Prabhat Jain,Deepak Tomar,Kashyap Garimella,V. Kamakoti +4 more
- pp 1-15
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TLDR
It is argued that Hardware Transactional Memory (HTM) can be a suitable implementation choice for these systems and the knowledge about the workload is extremely useful to make appropriate design choices in the workload optimized HTM.Abstract:
Workload optimized systems consisting of large number of general and special purpose cores, and with a support for shared memory programming, are slowly becoming prevalent. One of the major impediments for effective parallel programming on these systems is lock-based synchronization. An alternate synchronization solution called Transactional Memory (TM) is currently being explored.We observe that most of the TM design proposals in literature are catered to match the constrains of general purpose computing platforms. Given the fact that workload optimized systems utilize wider hardware design spaces and on-chip parallelism, we argue that Hardware Transactional Memory (HTM) can be a suitable implementation choice for these systems. We re-evaluate the criteria to be satisfied by a HTM and identify possible scope for relaxations in the context of workload optimized systems. Based on the relaxed criteria, we demonstrate the scope for building HTM design variants, such that, each variant caters to a specific workload requirement. We carry out suitable experiments to bring about the trade-off between the design variants. Overall, we show how the knowledge about the workload is extremely useful to make appropriate design choices in the workload optimized HTM.read more
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Journal ArticleDOI
Parallel Scientific Computation: A Structured Approach using BSP and MPI
TL;DR: This is the first textbook provides a comprehensive overview of the technical aspects of building parallel programs using BSP and BSPlib, and is contemporary, well presented, and balanced between concepts and the technical depth required for developing parallel algorithms.
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H.R. Srinivas,Keshab K. Parhi +1 more
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Hardware design and arithmetic algorithms for a variable-precision, interval arithmetic coprocessor
M.J. Schulte,E.E. Swartzlander +1 more
TL;DR: This paper presents the hardware design and arithmetic algorithms for a coprocessor that performs variable-precision, interval arithmetic that can be implemented on a single chip with a cycle time that is comparable to IEEE double- precision floating pointCoprocessors.