Reduced instruction set computing (RISC) architecture started as a fresh look at existing ideas. The main featue of RISC is the architectural support for the exploitation of parallelism on the instruction level. All distinguished features of RISC should be considered in light of their support for the RISC pipeline.


Keywords:

IBM 801;
RISC;
computer architecture;
load/store architecture;
instruction sets;
pipelining;
superscalar machines;
superpipeline machines;
optimizing compiler;
branch and execute;
delayed branch;
cache;
Harvard architecture;
delayed load;
superscalar;
superpipelined

/pdf/reduced-instruction-set-computing-233olupw5r.pdf

Reduced Instruction Set Computing

This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today. In this edition, the authors bring their trademark method of quantitative analysis not only to high-performance desktop machine design, but also to the design of embedded and server systems. They have illustrated their principles with designs from all three of these domains, including examples from consumer electronics, multimedia and Web technologies, and high-performance computing.

https://cds.cern.ch/record/1414394/files/9780123838728_TOC.pdf

Computer Architecture: A Quantitative Approach

Branch Prediction Strategies and Branch Target Buffer Design

This paper describes the methods employed in the floating-point area of the System/360 Model 91 to exploit the existence of multiple execution units. Basic to these techniques is a simple common data busing and register tagging scheme which permits simultaneous execution of independent instructions while preserving the essential precedences inherent in the instruction stream. The common data bus improves performance by efficiently utilizing the execution units without requiring specially optimized code. Instead, the hardware, by 'looking ahead' about eight instructions. automatically optimizes the program execution on a local basis.

The application of these techniques is not limited to floating-point arithmetic or System/360 architecture. It may be used in almost any computer having multiple execution units and one or more 'accumulators.' Both of the execution units, as well as the associated storage buffers, multiple accumulators and input /output buses, are extensively checked.

An efficient algorithm for exploiting multiple arithmetic units

Branch prediction strategies and branch target buffer design

1. RISC Architecture: An Overview. 2. MIPS Processor Architecture Overview. 3. CPU Instruction Set Summary. 4. Memory Management System. 5. Caches. 6. Exception Processing. 7. FPU Overview. 8. FPU Instruction Set Summary and Instruction Pipeline. 9. Floating Point Exceptions. Appendixes. Index.

Reduced Instruction Set Computing

References

Computer Architecture: A Quantitative Approach

Branch Prediction Strategies and Branch Target Buffer Design

An efficient algorithm for exploiting multiple arithmetic units

Branch prediction strategies and branch target buffer design

MIPS RISC architecture

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